JPS5881798U - PROM writer - Google Patents
PROM writerInfo
- Publication number
- JPS5881798U JPS5881798U JP17511381U JP17511381U JPS5881798U JP S5881798 U JPS5881798 U JP S5881798U JP 17511381 U JP17511381 U JP 17511381U JP 17511381 U JP17511381 U JP 17511381U JP S5881798 U JPS5881798 U JP S5881798U
- Authority
- JP
- Japan
- Prior art keywords
- selection line
- address
- address selection
- writer
- prom writer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のＦＲＯＭ書込み方式を説明するためのブ
ロック図、第２図は本考案の実施例を説明するためのブ
ロック図、である。
なお図において、Ｙ１〜Ｙ８・・・・・・デコーダ出力
、Ｑ１〜Ｑ８・・・・・・ＭＯ８ＦＥＴトランジスタ、
Ｓｌ・・・外部より入力されるテスト信・号、１，２・
・・・・・書込データ、３．４・・・・・・読出しデー
タ、５〜８・・・・・−ＯＲ論理回路、を示す。FIG. 1 is a block diagram for explaining a conventional FROM writing method, and FIG. 2 is a block diagram for explaining an embodiment of the present invention. In the figure, Y1 to Y8...decoder output, Q1 to Q8...MO8FET transistor,
Sl...Test signal/signal input from the outside, 1, 2...
. . . write data, 3.4 . . . read data, 5 to 8 . . . -OR logic circuit.
Claims (1)
ＯＭライターにおいて、データ書込み回路と、該データ
書込み回路に入力されるアドレス選択線との間に、前記
アドレス選択線と、外部よりのテスト、信号からなる論
理和回路とを設け、前記アドレス選択線が非選択時にお
いても外部よりのテスト信号により、該アドレスが選択
された状態とする手段を備えていることを特徴とするＦ
ＲＯＭライター。FR used in FROM where data can be written electrically
In the OM writer, an OR circuit consisting of the address selection line and an external test signal is provided between the data write circuit and the address selection line input to the data write circuit, and the address selection line is connected to the address selection line. The F is characterized by comprising means for setting the address to a selected state by an external test signal even when the address is not selected.
ROM writer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17511381U JPS5881798U (en) | 1981-11-25 | 1981-11-25 | PROM writer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17511381U JPS5881798U (en) | 1981-11-25 | 1981-11-25 | PROM writer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5881798U true JPS5881798U (en) | 1983-06-02 |
Family
ID=29967355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17511381U Pending JPS5881798U (en) | 1981-11-25 | 1981-11-25 | PROM writer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5881798U (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5562588A (en) * | 1978-10-31 | 1980-05-12 | Matsushita Electric Ind Co Ltd | Semiconductor memory circuit |
| JPS5651093A (en) * | 1979-09-28 | 1981-05-08 | Nec Corp | Semiconductor storage device |
| JPS5654694A (en) * | 1979-07-02 | 1981-05-14 | Mostek Corp | Semiifixed memory unit integrated circuit and method of programming same circuit |
| JPS56134390A (en) * | 1980-03-21 | 1981-10-21 | Fujitsu Ltd | Rom element |
-
1981
- 1981-11-25 JP JP17511381U patent/JPS5881798U/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5562588A (en) * | 1978-10-31 | 1980-05-12 | Matsushita Electric Ind Co Ltd | Semiconductor memory circuit |
| JPS5654694A (en) * | 1979-07-02 | 1981-05-14 | Mostek Corp | Semiifixed memory unit integrated circuit and method of programming same circuit |
| JPS5651093A (en) * | 1979-09-28 | 1981-05-08 | Nec Corp | Semiconductor storage device |
| JPS56134390A (en) * | 1980-03-21 | 1981-10-21 | Fujitsu Ltd | Rom element |
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