JPS58171556U - panel control device - Google Patents
panel control deviceInfo
- Publication number
- JPS58171556U JPS58171556U JP6660882U JP6660882U JPS58171556U JP S58171556 U JPS58171556 U JP S58171556U JP 6660882 U JP6660882 U JP 6660882U JP 6660882 U JP6660882 U JP 6660882U JP S58171556 U JPS58171556 U JP S58171556U
- Authority
- JP
- Japan
- Prior art keywords
- processing device
- panel
- register
- memory
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、本考案の一実施例のマイクロプロセッサ−Ｍ
Ｐを用いた処理装置に対するパネル制御装置の接続を示
した図、第２図は同じくマイクロプロセッサ−ＭＰとし
て８０８５Ａを採用した場合の制御信号生成回路の構成
を説明するための図である。
ＭＰ・・・マイクロプロセッサ−１ＡＢ・・・アドレス
バス、ＤＢ・・・データバス、ＣＢ・・・制御信号バス
、ＡＲ・・・アドレスレジスタ、ＷＤＲ・・・ライトデ
ータレジスタ、ＲＤＲ・・・リードデータレジスタ。FIG. 1 shows a microprocessor-M according to an embodiment of the present invention.
FIG. 2 is a diagram showing the connection of a panel control device to a processing device using a microprocessor-MP, and is a diagram for explaining the configuration of a control signal generation circuit when an 8085A is adopted as the microprocessor-MP. MP...Microprocessor-1AB...Address bus, DB...Data bus, CB...Control signal bus, AR...Address register, WDR...Write data register, RDR...Read data register.
Claims (1)
びレジスタの値の読み出し、書き込みを行うパネル制御
装置において、パネルスイッチ信号を受けて設定アドレ
スを保持するレジスタと、同じく書き込みデータを保持
するレジスタと、メモリ、レジスタからの読み出しデー
タを保持するレジスタと、パネルのスタートストップ信
号を受けて処理装置をスタート、ストップさせる回路と
、処理装置に対して要求をする制御信号を擬似的に受け
つけかつ処理装置の出力する制御信号と同じ信号を擬似
的に作り出す回路とから成り、上記アドレス、データ、
制御信号を処理装置の各パスラインにのせることにより
システムを動作させてメモリ、レジスタの読み出し、書
き込みを行うことを特徴とするパネル制御装置。In a panel control device that starts and stops a processing device and reads and writes values in memory and registers outside the processing device, there is a register that receives a panel switch signal and holds a set address, and a register that also holds write data. A register that holds data read from memory and registers, a circuit that starts and stops the processing device in response to a start/stop signal from the panel, and a circuit that pseudo-receives control signals that request the processing device and controls the processing device. It consists of a circuit that pseudo-generates the same signal as the control signal to be output, and the address, data,
A panel control device characterized in that a control signal is placed on each pass line of a processing device to operate the system and perform reading and writing of memory and registers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6660882U JPS58171556U (en) | 1982-05-10 | 1982-05-10 | panel control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6660882U JPS58171556U (en) | 1982-05-10 | 1982-05-10 | panel control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58171556U true JPS58171556U (en) | 1983-11-16 |
Family
ID=30076472
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6660882U Pending JPS58171556U (en) | 1982-05-10 | 1982-05-10 | panel control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58171556U (en) |
-
1982
- 1982-05-10 JP JP6660882U patent/JPS58171556U/en active Pending
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