JPS6095653U - data bus control device - Google Patents
data bus control deviceInfo
- Publication number
- JPS6095653U JPS6095653U JP18642183U JP18642183U JPS6095653U JP S6095653 U JPS6095653 U JP S6095653U JP 18642183 U JP18642183 U JP 18642183U JP 18642183 U JP18642183 U JP 18642183U JP S6095653 U JPS6095653 U JP S6095653U
- Authority
- JP
- Japan
- Prior art keywords
- data bus
- microprocessor
- control device
- bus control
- response
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012790 confirmation Methods 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Information Transfer Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はデータバス制御装置における従来の構成例を示
したブロック図、第２図は本考案にかかるデータバス制
御装置の一実施例の構成を示したーブロック薗、第３図
は第２図のデータバス制御装置の各信号のタイムチャー
トであり、ａはアドレスストローブ信号、ｂはクロック
の出力信号、Ｃ，ｄおよびｅはＱＷＡＩＴ、 ＩＷＡＩ
Ｔおよび２ＷＡＩＴのタイミングに対応したタイミング
信号、ｆはチップセレクト信号、ｇはＤＴＡＣＫ信号の
タイムチャートである。
−１０・・・マイクロプロセッサ、２０，２０．．２０
２・・・ディバイス、３０・・・非同期データバス、４
０・・・レジスタ、４１，４ｈｔ ４１２・・・設定
レジスタ、５０・・・制御回路。FIG. 1 is a block diagram showing a conventional configuration example of a data bus control device, FIG. 2 is a block diagram showing the configuration of an embodiment of a data bus control device according to the present invention, and FIG. 1 is a time chart of each signal of the data bus control device, where a is an address strobe signal, b is a clock output signal, C, d and e are QWAIT, IWAI
A timing chart of timing signals corresponding to T and 2WAIT timings, f is a chip select signal, and g is a DTACK signal. -10...Microprocessor, 20,20. ．． 20
2...Device, 30...Asynchronous data bus, 4
0...Register, 41,4ht 412...Setting register, 50...Control circuit.
Claims (1)
データバスにより接続されていてマイクロプロセッサか
らアクセスされたときにデータ処理を行なうディバイス
と、該ディバイスについてアクセスが開始されて力〜ら
応答するまでの応答時間が任意に設定されるレジスタと
、該レジスタからの信号を受けてアクセスが行なわれた
ディバイスについてその応答時間が経過したとこはでア
クセスに対する応答を示すデータ確認信号を前記マイク
ロプロセッサに送る制御回路とを具備したことを特徴と
するデータバス制御装置。A microprocessor, a device that is connected to the microprocessor via an asynchronous data bus and processes data when accessed by the microprocessor, and an arbitrary response time from when an access is initiated to when the device responds. and a control circuit that sends a data confirmation signal indicating a response to the access to the microprocessor when the response time for the device accessed in response to the signal from the register has elapsed. A data bus control device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18642183U JPS6095653U (en) | 1983-12-01 | 1983-12-01 | data bus control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18642183U JPS6095653U (en) | 1983-12-01 | 1983-12-01 | data bus control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6095653U true JPS6095653U (en) | 1985-06-29 |
Family
ID=30402666
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18642183U Pending JPS6095653U (en) | 1983-12-01 | 1983-12-01 | data bus control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6095653U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6375960A (en) * | 1986-09-19 | 1988-04-06 | Hitachi Ltd | logic LSI |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54527A (en) * | 1977-06-03 | 1979-01-05 | Hitachi Ltd | Control circuit for terminal unit |
| JPS55110324A (en) * | 1979-02-16 | 1980-08-25 | Nec Corp | Unit control circuit |
-
1983
- 1983-12-01 JP JP18642183U patent/JPS6095653U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54527A (en) * | 1977-06-03 | 1979-01-05 | Hitachi Ltd | Control circuit for terminal unit |
| JPS55110324A (en) * | 1979-02-16 | 1980-08-25 | Nec Corp | Unit control circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6375960A (en) * | 1986-09-19 | 1988-04-06 | Hitachi Ltd | logic LSI |
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