JPS58155698U

JPS58155698U - memory circuit

Info

Publication number: JPS58155698U
Application number: JP2459682U
Authority: JP
Inventors: 上野山　任司
Original assignee: 日本電気株式会社
Priority date: 1982-02-23
Filing date: 1982-02-23
Publication date: 1983-10-18

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図ａは従来の記憶回路の一例を示す回路図、同図す
は同図ａに示すメモ１月Ｃを示すブロック図、第２図は
本考案の一実施例を示す回路図である。１〜２Ｎ・・・・・・メモ１月Ｃ１１０・・・・・・デ
コード回路、１１〜１Ｎ・・・・・・デコード回路の入
力端子、４０・・・・・・デコード回路のチップイネー
ブル端子、１−１〜１−２Ｎ・・・・・・デコード回路
の出力端子、２０・・・・・・選択回路、２１〜２Ｎ・
・・・・・選択回路のコントロール端子、２−１〜２−
２Ｎ・・・・・・選択回路の入力端子、３１・・・・・
・メモリＩＣのデータの入力端子、３２・・・・・・メ
モＩＪＩｃのデータの出力端子、４１・・・・・・メモ
１月Ｃのチップイネーブル端子、４２・・・・・・メモ
リＩＣのライトイネーブル端子、１０１〜ＩＯＮ・・・
・・・アドレス端子、２０１〜２ＯＮ・・・・・・書き
込み用アドレス端子、３０１〜３ＯＮ・・・・・・読み
出し用アドレス端子、４０１・・・・・・書き込み信号
端子、４０２・・・・・・メモリイネーブル端子、５０
１・・・・・・データ入力端子、５０２・・・・・・デ
ータ出力端子。FIG. 1A is a circuit diagram showing an example of a conventional memory circuit, FIG. 1A is a block diagram showing a memo C shown in FIG. . 1~2N...Memo January C110...Decode circuit, 11~1N...Decode circuit input terminal, 40...Decode circuit chip enable terminal , 1-1 to 1-2N... Output terminal of decoding circuit, 20... Selection circuit, 21 to 2N.
...Control terminal of selection circuit, 2-1 to 2-
2N... Input terminal of selection circuit, 31...
- Memory IC data input terminal, 32...Memo IJIc data output terminal, 41...Memo January C chip enable terminal, 42...Memory IC data output terminal. Write enable terminal, 101~ION...
...Address terminal, 201-2ON... Address terminal for writing, 301-3ON... Address terminal for reading, 401... Write signal terminal, 402...・・Memory enable terminal, 50
1...Data input terminal, 502...Data output terminal.

Claims

[Scope of utility model registration request]

It has an address terminal for writing and an address terminal for reading, and input terminals for the data of a plurality of memo 1 month C are connected in parallel and are used as data input terminals, and output terminals for the data of the memo 1 month C are respectively connected to the selection circuit. Connect to the input terminal,
The output terminal of the selection circuit is a data output terminal, the read address terminal is connected to a control input terminal of the selection circuit, the write address terminal is connected to an input terminal of a decoding circuit, and a write signal terminal is connected. are connected to the chip enable terminal of the decoding circuit, the output terminals of the decoding circuit are respectively connected to the write enable terminal of the memory IC, and the chip and enable terminals of the memory IC are connected in parallel. configured as an enable terminal, selectively inputs a write pulse to the memo C by a signal ' applied to the decode circuit and the write address terminal, and applied to the selection circuit and the read address terminal. A memory circuit characterized in that data is selected and outputted from the output data of the memo January C by a signal.