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JPS5894197U - Information writing device - Google Patents

Information writing device

Info

Publication number
JPS5894197U
JPS5894197U JP18763681U JP18763681U JPS5894197U JP S5894197 U JPS5894197 U JP S5894197U JP 18763681 U JP18763681 U JP 18763681U JP 18763681 U JP18763681 U JP 18763681U JP S5894197 U JPS5894197 U JP S5894197U
Authority
JP
Japan
Prior art keywords
memories
writing device
information writing
holding circuit
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18763681U
Other languages
Japanese (ja)
Inventor
矢ケ部　喜俊
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP18763681U priority Critical patent/JPS5894197U/en
Publication of JPS5894197U publication Critical patent/JPS5894197U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の書込器の構成図、第２図は本考案の一実
施例を示す構成図である。 １．１０・・・・・・アドレス保持装置、２．２０〜２
３・・・・・・データ保持回路、３，３０・・・・・・
制御装置、４．４０・・・・・・制御信号、５０．５１
−２〜５ｎ・・・・・・ＰＲＯＭ０　　　　− ７３０　　　　　ｙ１０FIG. 1 is a block diagram of a conventional writer, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1.10... Address holding device, 2.20~2
3... Data holding circuit, 3, 30...
Control device, 4.40... Control signal, 50.51
-2~5n...PROM0 - 730 y10

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数個のメモリに対して共通に用いられるアドレス保持
回路と、前記メモリ毎に設けられた書込情報保持回路と
を有し、前記書込情報保持回路に設定されている情報を
対応する前記複数個のメモリに同時はに書込むようにし
たことを特徴とする情報書込み器。It has an address holding circuit commonly used for a plurality of memories and a write information holding circuit provided for each of the memories, and the information set in the write information holding circuit is stored in the corresponding plurality of memories. An information writer characterized in that it writes to multiple memories at the same time.
JP18763681U 1981-12-16 1981-12-16 Information writing device Pending JPS5894197U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18763681U JPS5894197U (en) 1981-12-16 1981-12-16 Information writing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18763681U JPS5894197U (en) 1981-12-16 1981-12-16 Information writing device

Publications (1)

Publication Number Publication Date
JPS5894197U true JPS5894197U (en) 1983-06-25

Family

ID=30102771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18763681U Pending JPS5894197U (en) 1981-12-16 1981-12-16 Information writing device

Country Status (1)

Country Link
JP (1) JPS5894197U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55150194A (en) * 1979-05-04 1980-11-21 Ricoh Co Ltd Multiple write system in prom writer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55150194A (en) * 1979-05-04 1980-11-21 Ricoh Co Ltd Multiple write system in prom writer

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