JPS5725045A - Data processing equipment - Google Patents

Abstract

PURPOSE:To decrease the number of times of retransmission of an ineffective instruction, by constituting an information register for receiving an instruction from a CPU, having a multiple stack structure, in an additional processing equipment which is connected with a single bus. CONSTITUTION:In a memory device 2 is stored a program consisting of a series of instructions, a CPU3 reads out this instruction through a single bus 1, and when the instruction is an additional processing instruction, an instruction transfer signal and an operand transfer signal are sent to an additional processing equipment 4' through the bus 1. The equipment 4' contains an answering circuit 41 for answering to a request through the bus 1, an information register group 42' having plural stack structures consisting of an instruction register for storing an operating instruction from the CPU3, an operand address register, etc., and an operation part 43 for executing the additional processing instruction. In case when an instruction has been outputted continuously from the CPU3, this instruction is stored in order to the register group 42', and although a busy signal is generated in the course of processing of the instruction in the operation part 43, the instruction from the CPU is received so long as the register group 42' is available, and when the register group becomes full, a refusal instruction signal is outputted to the instruction of the CPU.