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JPS5552161A - Information processing system - Google Patents

Information processing system

Info

Publication number
JPS5552161A
JPS5552161A JP11876778A JP11876778A JPS5552161A JP S5552161 A JPS5552161 A JP S5552161A JP 11876778 A JP11876778 A JP 11876778A JP 11876778 A JP11876778 A JP 11876778A JP S5552161 A JPS5552161 A JP S5552161A
Authority
JP
Japan
Prior art keywords
count
instruction
pulse
information processing
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11876778A
Other languages
Japanese (ja)
Inventor
Yoshiro Ikegami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11876778A priority Critical patent/JPS5552161A/en
Publication of JPS5552161A publication Critical patent/JPS5552161A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To enable to measure the idling condition time of resource in the system easily, by using the count set counting the idling state of information processor.
CONSTITUTION: The information processor 1 consists of the instruction pick up set 2 producing the operation instruction based on the instruction word picked up from the main memory unit, instruction execution set 3 performing operation based on the instruction, conventional register set 4 connected to it, communication means required on the execution of program among other units in the information processing system, and the count set 5 counting it with the count pulse when the information processing unit 1 is not used as the resource in the system. Further, the count set 5 consists of the pulse generator 27 generating the count pulse 16, temporary memory register 20, and adder 21, and "1" is added to the content of the register 20 at the added by the count instruction 15 every time the pulse 16 is logical "1" when the count effective signal 14 is at logical "1".
COPYRIGHT: (C)1980,JPO&Japio
JP11876778A 1978-09-26 1978-09-26 Information processing system Pending JPS5552161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11876778A JPS5552161A (en) 1978-09-26 1978-09-26 Information processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11876778A JPS5552161A (en) 1978-09-26 1978-09-26 Information processing system

Publications (1)

Publication Number Publication Date
JPS5552161A true JPS5552161A (en) 1980-04-16

Family

ID=14744554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11876778A Pending JPS5552161A (en) 1978-09-26 1978-09-26 Information processing system

Country Status (1)

Country Link
JP (1) JPS5552161A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58195919A (en) * 1982-05-11 1983-11-15 Fujitsu Ltd Estimated output time display method for output file

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58195919A (en) * 1982-05-11 1983-11-15 Fujitsu Ltd Estimated output time display method for output file

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