JPH02137002A - High-speed sequence arithmetic processing device - Google Patents

Abstract

PURPOSE:To improve the soft production efficiency of a process where the sequence logical arithmetic and the numerical arithmetic are mixed by describing the sequence logical arithmetic with a transfer instruction of a macroprocessor. CONSTITUTION:A processor 1 stores the state value, the arithmetic result, etc., of a plant into a memory 11. A bit segmenting/embedding part 12 segments the operation bit to be processed by a sequence logical arithmetic part 17 out of the data of the memory 11 and at the same time embeds the data bit information into the memory 11 with the instruction of an instruction decoder 15. The arithmetic information given from an MPU 2 is decoded by the decoder 15 and stored in an instruction queue 14. Then the sequence arithmetic information stored in the queue 14 is counted by an instruction counter 18. When the count value of the counter 18 reaches the limit level of the queue 14, the counter sends an information transmission inhibiting signal to the MPU 2.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a device that performs sequence logic operations and numerical operations, and in particular, a high-speed device suitable for performing sequence logic 2 calculations at high speed using a microprocessor. The present invention relates to a sequence arithmetic processing device.

[Conventional technology]

As discussed in Japanese Patent Application Laid-Open No. 105505/1983, a conventional device for performing sequence logic operations and numerical operations is realized using a dedicated circuit that processes sequence instructions using hardware and processes numerical operations using micro programs. It was something to do.

However, the progress of microprocessors in recent years has been remarkable, and from the point of view of low cost and high performance of microprocessors,
There is a trend to apply microprocessors to devices that were previously realized using dedicated circuits to achieve lower costs and higher performance.

Even in devices that perform sequence logical operations and numerical operations,
It is desired to realize a processing device using a microprocessor from the viewpoint of the high efficiency thi (rationality) of numerical operations of the microprocessor.

[All the problems that the invention attempts to solve]

The conventional technology does not take into consideration the application of a microprocessor to a sequence calculation device, and has the problem of not being in line with recent technological trends.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed sequence arithmetic processing device that enables high-speed execution of processing in which sequence logical operations and numerical operations are mixed using a microprocessor.

[Means to solve the problem]

In order to achieve the above object, the high-speed sequence arithmetic processing device according to the present invention causes the central processing unit to output sequence logical operation information, executes the sequence logical operation based on the information, and stores the sequence logical operation information. means for counting the accumulated number of sequence logical operation information; means for decoding and executing the sequence logical operation information; means for storing data; and means for embedding in the central processing unit and peripheral devices.

Then, when the count becomes zero, a means is added to the counting means to notify the central processing unit of the completion of the sequence logical operation, and when the central processing unit outputs the sequence operation information, it is executed by a transfer command, and the central processing The device shall be provided with transfer command means.

[Effect]

According to the present invention, the sequence operation information queue of the high-speed sequence operation processing device sequentially stores sequence operation information that is continuously transferred from the microprocessor. The sequence operation information is decoded and executed in the order of arrival.

Furthermore, when all the sequence logical operations in the sequence operation information queue have been executed, the means for notifying the completion of sequence logical operations indicates that the execution of all the sequence operation information transferred by the microprocessor has been completed. The microprocessor uses the 1 notification means to confirm that the execution of the sequence logical operation has been completed, and then starts execution of the next operation.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 1 to 6.

As shown in FIGS. 1 and 2, a means for causing the central processing unit (microprocessor) 2 to output sequence logical operation information, executes the sequence logical operation based on the information, and accumulates the sequence logical operation information. (instruction queue) 14, means for counting the accumulated number of sequence logic operation information (instruction counter) 18, means for decoding and executing sequence logic operation information (instruction decoder) 15, and means for storing data (memory) 11 and a means (bit extraction/embedding part) 12 for extracting operation bits from the data and embedding the operation bits at arbitrary positions in the data, and is configured to be provided together with the central processing unit 2 and peripheral devices. .

Then, a means (data bus) 33 is added to the counting means (instruction counter) 18 to notify the central processing unit 2 of the completion of the sequence logic operation when the count reaches zero, and the sequence operation information is sent from the central processing unit 2. When outputting, it is executed by a transfer command, and the transfer command means 3 is sent to the central processing unit 2.
5 shall be provided.

The plant controller 100 includes a high-speed sequence processing device 1. Microprocessor 2, plant controller 1
00, a memory 4 which stores data necessary for the processing, an interface section 5 with the system bus 200, and an internal path 3 connecting these.

The plant controller 100 then uses the system bus 2
00, a process output device 300 that transmits the control amount from the plant controller 100 to the plant 600;
The state quantity of the plant 600 is transferred to the plant controller 100.
Process input device 400 and plant 600
It is connected to a process input/output device 500 that transmits state quantities to the brand controller 100 and transmits controlled quantities from the plant controller 100 to the plant 600.

The plant controller 1.00 inputs the state quantities of the plant 600 using the process input device 400 and the process input/output device 500 based on the program stored in the memory 4, and executes numerical calculations, sequence calculations, etc. A control amount is calculated, and this control amount is sent to the process output device 300.
and the plant 600 using the process input/output device 500
Execute the process to send to.

This process is based on various theories of discrete system control and is completed within one control cycle of the plant.

FIG. 2 shows the internal configuration of the high-speed sequence arithmetic processing device 1 of the present invention.

The high-speed sequence processing device 1 and the microprocessor 2 are connected by an internal bus 3 consisting of a control bus 31, an address bus 32, and a data bus 33.

The high-speed sequence processing device 1 extracts operation bits to be processed by the sequence logic operation unit 17 from the data in the memory 11 according to instructions from a memory 11 that stores state quantities of the plant, operation results, etc. and an instruction decoder 15.
A bit extraction/embedding unit 12 that embeds bit information into the data in the memory 11 according to instructions from the memory 11; a memory address decoder 13; an instruction queue 14 that stores operation information from the microprocessor 2; Instruction decoder 15 for decoding information. Bit accumulator 16, sequence logic operation unit 17, instruction queue 14
The instruction counter 18 is provided to count the number of sequence operation information stored in the instruction counter 18.

The sequence calculation information is transmitted to the high-speed sequence calculation processing device 1 via the data bus 33 in response to a transfer command from the microprocessor 2.

The instruction queue 14 and the instruction counter 18 are cleared to zero when the system is started up, and each time one piece of sequence operation information from the microprocessor 2 is accumulated in the instruction queue 14, the instruction counter 18 is incremented. Each time one piece of calculation information is sent to the decoder 15, the instruction counter 18 is decremented.

The instruction counter 18 activates a calculation information transmission prohibition signal to the microprocessor 2 when the count reaches the limit number that can be stored in the instruction queue 14, and deactivates the calculation information transmission prohibition signal when the count falls below the limit number.

Further, the instruction counter 18 indicates that the count of the instruction queue 14 is 0.
When this happens, a computation end interrupt is sent to the microprocessor 2.

FIG. 3 shows an example of the transfer instruction format (transfer instruction means) 35 of the microprocessor 2 and the sequence operation information transferred to the high-speed sequence operation processing device 1 by the transfer instruction.

FIG. 3 shows the format of a transfer command for the microprocessor 2, which is composed of a transfer instruction code bit, a transfer destination address bit, and 32 bits of transfer data.

FIG. 4 shows the sequence operation information format of the high-speed sequence operation processing device 1, which includes a 5-bit instruction code indicating the type of sequence operation information, 16 bits of the operation target data address, and 4 bits indicating the operation bit position in the data. total of 2
It consists of 5 pits.

According to this embodiment, the microprocessor 2 receives and executes the transfer instruction shown in FIG. 3 from the memory 4 shown in FIG. Transfer to arithmetic processing unit 1,
It is possible to cause the high-speed sequence arithmetic processing device 1 to execute sequence logical operations.

FIG. 5 shows an example of a program executed by the plant controller 100.

This program is POL (Problem O
Each symbol surrounded by a dotted line in the figure indicates a different function.

In the figure, 1001 is a load instruction, which represents the process of transferring the contents of the memory 11 to the accumulator.

In the figure, reference numeral 1002 is a comparison instruction, which compares the contents of the accumulator with the contents of a designated address, and if the value is larger, sets the bit accumulator 16 to 1, and otherwise sets it to 0.

1003 in the figure is AND, pit accumulator 1
6 and the operation bit of the memory 11, and sets it in the bit accumulator 16.

In the figure, 1004 is Complete+++ent And, which takes the AND of the pit accumulator 16 and the inverted value of the operation bit of the memory 11, and
6 represents the process of setting.

In the figure, 1005 is the output, and the pit accumulator 16
represents the process of storing the contents of 1 to 1 in the designated bits of the memory 11.

FIG. 6 shows the operation of the microprocessor 2 and high-speed sequence arithmetic processing device 1 when executing the program shown in FIG.

The microprocessor 2 takes in the state quantity of the plant at the beginning of the process, and stores it in the memory 11 included in the high-speed sequence arithmetic processing device 1 (2001).

The data to be calculated is transferred from the memory 11 to the microprocessor 2.
(2002).

Compare the specified data and the value of the accumulator (
2003).

If the comparison result is true, the sequence command (Figure 5
The sequence calculation information 2008 of 003) is sent to the instruction queue 14 of the high-speed sequence calculation processing device 1 by a transfer command (2004).

Thereafter, the microprocessor 2 continuously transfers the sequence instruction operation information 2009 and 2010 to the high-speed sequence operation processing device 1 until a numerical operation instruction appears in the program or until the end of the program (2005 and 2006).

Instruction queue 1 included in high-speed sequence arithmetic processing device 1
4 is FIF○ (First In First 0u
t) Because of the structure, the sequence operation information 2008.2009.2010 is transmitted to the sequence logic operation unit 17 included in the high-speed sequence operation processing device 1 in the order in which the microprocessor 2 sends out the sequence operation information 2008.2009.2010, thereby enabling sequential execution ( 2011.2012.2013).

The last sequence instruction 20 in the sequence logic operation unit 17
13, a computation end interrupt is sent to the microprocessor 2.

As a result, the microprocessor 2 performs the next process (in this embodiment, the output 20 of the plant control amount from the memory 11
07).

Note that the configuration of the internal bus, the number of registers,
The calculation information format and the program to be executed are unique to this embodiment, and do not limit the present invention.

According to this embodiment, sequence logical operations can be written in the same language as the microprocessor.

This eliminates the need for the programmer to pay attention to the synchronization between the sequence logic operation circuit and the microprocessor even for processing in which sequence logic operations and numerical operations are mixed, which has the effect of improving software production efficiency.

Further, by providing the high-speed sequence arithmetic processing device with an instruction queue, the microprocessor can continuously transmit sequence arithmetic information.

As a result, the microprocessor can perform other processing until the sequence logic operation is completed in the high-speed sequence operation/processing device after continuously transmitting the sequence operation information, which has the effect of increasing the efficiency and speed of processing. .

〔Effect of the invention〕

According to the present invention, the high-speed sequence arithmetic processing device allows sequence logic operations to be described using transfer instructions of a microprocessor, so that even for processing in which sequence logic operations and numerical operations are mixed, the programmer can use the sequence logic operation This eliminates the need to pay attention to the synchronization of numerical calculation circuits, which has the effect of improving software production efficiency.

Further, all sequence logic operation instructions can be executed by a transfer instruction of the microprocessor, and furthermore, by providing the high-speed sequence operation processing device with an instruction queue, the microprocessor can continuously transmit sequence operation information.

As a result, the microprocessor can perform other processing after continuously transmitting sequence operation information until the sequence logic operation is completed in the high-speed sequence operation processing unit, which has the effect of increasing the efficiency and speed of processing. .

Furthermore, it is possible to realize a low-cost, high-performance device that performs sequence logic operations and numerical operations using a microprocessor.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram showing an embodiment of the present invention, FIG. 2 is an internal configuration diagram of the main parts shown in FIG. 1, and FIG. 3 is an embodiment of the transfer instruction format from a microprocessor. figure,
FIG. 4 is a diagram showing an example of the sequence calculation information format;
FIG. 5 is a diagram showing an example of a program executed by the plant controller, and FIG. 6 is a diagram illustrating details of the microprocessor and the present invention when executing the program shown in FIG. 5. 1...High-speed sequence arithmetic processing device. 2...Microprocessor (central processing unit), 11.
...Memory (means for storing), 12... Pit cutting/filling section (means for filling) 14
... instruction queue (means for accumulating), 15 ... instruction decoder (means for decoding and executing), 18 ... instruction counter (means for counting), 33 ... data bus (means for notifying), 35. ...Transfer command means.

Claims (1)

[Claims] 1. Cause the central processing unit to output sequence logical operation information and execute the sequence logical operation based on the information,
means for accumulating the sequence logic operation information, means for counting the number of accumulated sequence logic operation information, means for decoding and executing the sequence logic operation information, means for storing data, and extracting operation bits from the data. A high-speed sequence arithmetic processing device, characterized in that it is provided together with the central processing unit and peripheral devices, and includes means for extracting and embedding the manipulated bits in arbitrary positions of the data. 2. The high-speed sequence arithmetic processing device according to claim 1, wherein the counting means further includes means for notifying the central processing unit of the completion of the sequence logic operation when the count reaches zero. 3. The high-speed sequence arithmetic processing device according to claim 1, wherein the output of the sequence arithmetic information from the central processing unit is executed by a transfer command, and the central processing unit is provided with a transfer command means.