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JPS5692666A - Reserve system for input and output device - Google Patents

Reserve system for input and output device

Info

Publication number
JPS5692666A
JPS5692666A JP16989379A JP16989379A JPS5692666A JP S5692666 A JPS5692666 A JP S5692666A JP 16989379 A JP16989379 A JP 16989379A JP 16989379 A JP16989379 A JP 16989379A JP S5692666 A JPS5692666 A JP S5692666A
Authority
JP
Japan
Prior art keywords
instruction
index
reserve
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16989379A
Other languages
Japanese (ja)
Inventor
Kazuo Kumagai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16989379A priority Critical patent/JPS5692666A/en
Publication of JPS5692666A publication Critical patent/JPS5692666A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To enable to reserve an input and output device in OS unit without hindrance, by executing the instruction of OS index reserved only, in the input and output device in common use from a plurality of operation systems OSs.
CONSTITUTION: When the index is input together with the reserve instruction from OS of the upper rank device 20, the index is recognized and stored in the reserve memory circuit 24 with the reserve instruction. The reserve OS index read out from the memory circuit 24 is compared with the index output fed from the same OS later and if in agreement, the input and output instruction signal from the instruction reception circuit 21 is output as the operating signal. Further, the operating signal is output similarly, when no reserve index is present. Further, if the instruction is given from the OS other than the reserved OS, disagreement signal is output and the signal in use is fed for response. At the input and output device side, based on the OS index, the instruction of the reserved OS is executed, and the signal in use is responded to the instruction of the OS not reserved to prevent the misprocessing.
COPYRIGHT: (C)1981,JPO&Japio
JP16989379A 1979-12-26 1979-12-26 Reserve system for input and output device Pending JPS5692666A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16989379A JPS5692666A (en) 1979-12-26 1979-12-26 Reserve system for input and output device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16989379A JPS5692666A (en) 1979-12-26 1979-12-26 Reserve system for input and output device

Publications (1)

Publication Number Publication Date
JPS5692666A true JPS5692666A (en) 1981-07-27

Family

ID=15894908

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16989379A Pending JPS5692666A (en) 1979-12-26 1979-12-26 Reserve system for input and output device

Country Status (1)

Country Link
JP (1) JPS5692666A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61226842A (en) * 1985-03-30 1986-10-08 Nec Corp Resources control system for electronic computer system
JPH04199355A (en) * 1990-11-29 1992-07-20 Hitachi Ltd Attached processor system
WO1997009674A1 (en) * 1995-09-01 1997-03-13 Hitachi, Ltd. Data processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61226842A (en) * 1985-03-30 1986-10-08 Nec Corp Resources control system for electronic computer system
JPH04199355A (en) * 1990-11-29 1992-07-20 Hitachi Ltd Attached processor system
WO1997009674A1 (en) * 1995-09-01 1997-03-13 Hitachi, Ltd. Data processor

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