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JPS567129A - Device selection circuit - Google Patents

Device selection circuit

Info

Publication number
JPS567129A
JPS567129A JP8369179A JP8369179A JPS567129A JP S567129 A JPS567129 A JP S567129A JP 8369179 A JP8369179 A JP 8369179A JP 8369179 A JP8369179 A JP 8369179A JP S567129 A JPS567129 A JP S567129A
Authority
JP
Japan
Prior art keywords
output
circuit
card
referred
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8369179A
Other languages
Japanese (ja)
Inventor
Yutaka Nishikado
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8369179A priority Critical patent/JPS567129A/en
Publication of JPS567129A publication Critical patent/JPS567129A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To ensure the assured selection for the device through a low-cost constitution, by inhibiting the simultaneous output of the answers from two devices.
CONSTITUTION: The chainlike connection is secured for the inputs of the single side of answer signal generating circuit 6 which uses the exclusive logic sum of two inputs for the basic circuit. And the input of device card 2 which is most distant from computer 1 is connected to logic "0"; and the output of card 2 nearest computer 1 functions as the overall answer signal respectively. The output of address coincidence circuit 5 card 2 of No.i from the side of computer 1 among n-sheets of card 2 is referred to as ai; while the other external output not to be connected to ai of circuit 6 is referred to as bi along with the output of circuit 6 referred to as ci each. Thus ai is "1" only when the coincidence is secured among the device addresses; and b=ci+1 is obtained since the chainlike connection is given to circuit 6. And in case i is varied in 1Wn and one of aiWan is "1", output ci becomes "1". While ci becomes "0" when two of aiWan are 1 simultaneously. Thus the answer signal is inhibited.
COPYRIGHT: (C)1981,JPO&Japio
JP8369179A 1979-06-29 1979-06-29 Device selection circuit Pending JPS567129A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8369179A JPS567129A (en) 1979-06-29 1979-06-29 Device selection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8369179A JPS567129A (en) 1979-06-29 1979-06-29 Device selection circuit

Publications (1)

Publication Number Publication Date
JPS567129A true JPS567129A (en) 1981-01-24

Family

ID=13809509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8369179A Pending JPS567129A (en) 1979-06-29 1979-06-29 Device selection circuit

Country Status (1)

Country Link
JP (1) JPS567129A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6024661A (en) * 1983-07-20 1985-02-07 Hitachi Ltd Interlocking method of input/output card
JPH03115309U (en) * 1990-03-09 1991-11-28

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6024661A (en) * 1983-07-20 1985-02-07 Hitachi Ltd Interlocking method of input/output card
JPH03115309U (en) * 1990-03-09 1991-11-28

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