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JPS5562771A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS5562771A
JPS5562771A JP13445578A JP13445578A JPS5562771A JP S5562771 A JPS5562771 A JP S5562771A JP 13445578 A JP13445578 A JP 13445578A JP 13445578 A JP13445578 A JP 13445578A JP S5562771 A JPS5562771 A JP S5562771A
Authority
JP
Japan
Prior art keywords
layers
oxide films
poly
masks
speeds
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13445578A
Other languages
Japanese (ja)
Inventor
Tetsuya Iizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13445578A priority Critical patent/JPS5562771A/en
Publication of JPS5562771A publication Critical patent/JPS5562771A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Landscapes

  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To obtain a gate, which operates at high-speeds, and a memory cell with a high integrating degree of minute memory holding currents, by forming a source, a drain and a channel in poly Si layers made up on an insulator. CONSTITUTION:A P well 20 is manufactured on an N substrate 10, thermal oxide films 70-90 are built up by etching the substrate 10 by using the masks of SiO230, 40 and Si3N450, 60 and the masks are removed. Gate oxide films 111, 112 are mounted, non-addition poly Si layers 100, 110, 120 and 130 are selectively formed and a non-addition poly Si layer 114 is placed through oxide films. Layers 140, 150 are prepared by choicely removing the layer 114, and phosphor-added Sio2 is selectively laminated. P-layers 120, 160, 170, 13a, 150 and 13b are manufactured by diffusing B, and N-layers 10a, 140, 10b, 180, 110 and 190 are prepared by diffusing phosphor. And when these layers are covered with an oxide film, windows are opened and an Al electrode is attached, a C-MOS and a memory are simultaneously made up. According to this constitution, a high integrating degree is obtained at high-speeds, conduction currents are lessened and a suitable memory cell is acquired.
JP13445578A 1978-11-02 1978-11-02 Integrated circuit device Pending JPS5562771A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13445578A JPS5562771A (en) 1978-11-02 1978-11-02 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13445578A JPS5562771A (en) 1978-11-02 1978-11-02 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5562771A true JPS5562771A (en) 1980-05-12

Family

ID=15128732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13445578A Pending JPS5562771A (en) 1978-11-02 1978-11-02 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5562771A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5760868A (en) * 1980-09-29 1982-04-13 Seiko Epson Corp Cmos memory cell
JPS57192069A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Insulated gate field effect semiconductor device
US4593453A (en) * 1982-06-01 1986-06-10 Rockwell International Corporation Two-level transistor structures and method utilizing minimal area therefor
US4635089A (en) * 1981-10-28 1987-01-06 Kabushiki Kaisha Daini Seikosha MIS-integrated semiconductor device
US4799097A (en) * 1987-07-29 1989-01-17 Ncr Corporation CMOS integrated devices in seeded islands
JPH0214564A (en) * 1989-04-10 1990-01-18 Seiko Epson Corp CMOS memory cell
JPH0214566A (en) * 1989-04-10 1990-01-18 Seiko Epson Corp flip flop
JPH0221656A (en) * 1989-04-10 1990-01-24 Seiko Epson Corp Cmos memory cell
JPH0221655A (en) * 1989-04-10 1990-01-24 Seiko Epson Corp flip flop
JPH08213482A (en) * 1995-11-24 1996-08-20 Seiko Epson Corp Method for manufacturing thin film transistor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5055281A (en) * 1973-09-12 1975-05-15

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5055281A (en) * 1973-09-12 1975-05-15

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5760868A (en) * 1980-09-29 1982-04-13 Seiko Epson Corp Cmos memory cell
JPS57192069A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Insulated gate field effect semiconductor device
US4635089A (en) * 1981-10-28 1987-01-06 Kabushiki Kaisha Daini Seikosha MIS-integrated semiconductor device
US4593453A (en) * 1982-06-01 1986-06-10 Rockwell International Corporation Two-level transistor structures and method utilizing minimal area therefor
US4799097A (en) * 1987-07-29 1989-01-17 Ncr Corporation CMOS integrated devices in seeded islands
JPH0214564A (en) * 1989-04-10 1990-01-18 Seiko Epson Corp CMOS memory cell
JPH0214566A (en) * 1989-04-10 1990-01-18 Seiko Epson Corp flip flop
JPH0221656A (en) * 1989-04-10 1990-01-24 Seiko Epson Corp Cmos memory cell
JPH0221655A (en) * 1989-04-10 1990-01-24 Seiko Epson Corp flip flop
JPH08213482A (en) * 1995-11-24 1996-08-20 Seiko Epson Corp Method for manufacturing thin film transistor

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