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JPS5642372A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5642372A
JPS5642372A JP11707479A JP11707479A JPS5642372A JP S5642372 A JPS5642372 A JP S5642372A JP 11707479 A JP11707479 A JP 11707479A JP 11707479 A JP11707479 A JP 11707479A JP S5642372 A JPS5642372 A JP S5642372A
Authority
JP
Japan
Prior art keywords
film
region
diffused
oxide film
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11707479A
Other languages
Japanese (ja)
Inventor
Shiyouji Ariizumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11707479A priority Critical patent/JPS5642372A/en
Publication of JPS5642372A publication Critical patent/JPS5642372A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To reduce the contact hole area of the semiconductor device and to increase the integrity of the device by laminating a polycrystalline Si film and an Si3N4 film including impurity corresponding to the diffused regions when forming electrode wires in the device and opening a window of predetermined size to form a diffused region therein. CONSTITUTION:A thick field oxide film 22 is formed on the periphery of a P type Si substrate 21, a thin gate oxide film 23 is coated on an MOSFET forming region surrounded thereby, and contact holes 24, 25 are opened at both ends thereof. Then, an N type polycrystalline Si film 26 and an Si3N4 film 27 are laminated on the whole surface, are etched, and the laminate is retained only on the center region of the film 23 within one hole 24, and the others are removed. Subsquently, with them as mask an N<+> type source region 31 and drain region 32 are diffused in the substrate 21, impurity in the film 26 is diffused simultaneously in the hole 24, and a shallow source region reaching the region 31 is formed. Thereafter, an oxide film 33 is covered on the entire surface, holes are opened thereat, and electrodes 34-36 are covered on the respective regions.
JP11707479A 1979-09-12 1979-09-12 Manufacture of semiconductor device Pending JPS5642372A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11707479A JPS5642372A (en) 1979-09-12 1979-09-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11707479A JPS5642372A (en) 1979-09-12 1979-09-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5642372A true JPS5642372A (en) 1981-04-20

Family

ID=14702756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11707479A Pending JPS5642372A (en) 1979-09-12 1979-09-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5642372A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5941870A (en) * 1982-08-25 1984-03-08 Toshiba Corp Manufacturing method of semiconductor device
US5670397A (en) * 1997-01-16 1997-09-23 Powerchip Semiconductor Corp. Dual poly-gate deep submicron CMOS with buried contact technology

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52153382A (en) * 1976-06-15 1977-12-20 Matsushita Electric Ind Co Ltd Preparation of semiconductor device
JPS52153384A (en) * 1976-06-15 1977-12-20 Matsushita Electric Ind Co Ltd Preparation of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52153382A (en) * 1976-06-15 1977-12-20 Matsushita Electric Ind Co Ltd Preparation of semiconductor device
JPS52153384A (en) * 1976-06-15 1977-12-20 Matsushita Electric Ind Co Ltd Preparation of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5941870A (en) * 1982-08-25 1984-03-08 Toshiba Corp Manufacturing method of semiconductor device
JPH0576177B2 (en) * 1982-08-25 1993-10-22 Tokyo Shibaura Electric Co
US5670397A (en) * 1997-01-16 1997-09-23 Powerchip Semiconductor Corp. Dual poly-gate deep submicron CMOS with buried contact technology

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