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JPS55154645A - Test unit - Google Patents

Test unit

Info

Publication number
JPS55154645A
JPS55154645A JP6287379A JP6287379A JPS55154645A JP S55154645 A JPS55154645 A JP S55154645A JP 6287379 A JP6287379 A JP 6287379A JP 6287379 A JP6287379 A JP 6287379A JP S55154645 A JPS55154645 A JP S55154645A
Authority
JP
Japan
Prior art keywords
terminal
ram11
data
fed
operational processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6287379A
Other languages
Japanese (ja)
Inventor
Yoshiaki Bandai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6287379A priority Critical patent/JPS55154645A/en
Publication of JPS55154645A publication Critical patent/JPS55154645A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To enable to diagnose the operational processor with a suitable program quickly, by providing reloadable memory, storing an arbitrary diagnosis program in this memory and executing the diagnosis program.
CONSTITUTION: A reloadable RAM11 is provided with a data input terminal DI, data output terminal DO, write-in terminal W, address input terminal A and chip selection terminal CS, and the data write-in signal G3 from a control circuit 12 producing the timing of the circuits including each operational processor is fed to the terminal W. Further, the address input from the address switching circuit 14 designating the address of RAM11 is fed to the terminal A, the data from the data switching circuit 13 is fed to the terminal DI, and the output of an exclusive control circuit 15 selecting either of RAM11 or ROM in the operational processor is fed to the terminal CS, and the data signal RDL from the output terminal DO of RAM11 is output to external instruction register and a display circuit 17. Further, the operational processor can quickly be tested with the optimum program stored in the RAM11.
COPYRIGHT: (C)1980,JPO&Japio
JP6287379A 1979-05-22 1979-05-22 Test unit Pending JPS55154645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6287379A JPS55154645A (en) 1979-05-22 1979-05-22 Test unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6287379A JPS55154645A (en) 1979-05-22 1979-05-22 Test unit

Publications (1)

Publication Number Publication Date
JPS55154645A true JPS55154645A (en) 1980-12-02

Family

ID=13212814

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6287379A Pending JPS55154645A (en) 1979-05-22 1979-05-22 Test unit

Country Status (1)

Country Link
JP (1) JPS55154645A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100394135B1 (en) * 1995-09-11 2003-10-11 교토지도기키 가부시키가이샤 Weighing scale for granule

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100394135B1 (en) * 1995-09-11 2003-10-11 교토지도기키 가부시키가이샤 Weighing scale for granule

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