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JPS5563432A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS5563432A
JPS5563432A JP13695678A JP13695678A JPS5563432A JP S5563432 A JPS5563432 A JP S5563432A JP 13695678 A JP13695678 A JP 13695678A JP 13695678 A JP13695678 A JP 13695678A JP S5563432 A JPS5563432 A JP S5563432A
Authority
JP
Japan
Prior art keywords
signal line
line
address signal
test
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13695678A
Other languages
Japanese (ja)
Other versions
JPS6211382B2 (en
Inventor
Toshi Sano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13695678A priority Critical patent/JPS5563432A/en
Publication of JPS5563432A publication Critical patent/JPS5563432A/en
Publication of JPS6211382B2 publication Critical patent/JPS6211382B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Microcomputers (AREA)
  • Executing Machine-Instructions (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To prevent the increase in the number of terminals, by enabling, to test the inner memory directly without through the processor and by commonly using the buffer provided for normal operation and test operation.
CONSTITUTION: The circuit 200 consists of the random logic section 201, memory control circuit 202, RAM 203, ROM 204, buffer sections 228 and 229, and selection circuits 215 and 216. Further, the circuit 202 is connected with the control signal line 205 and address signal line 206, and the RAM 203 is connected with the memory enable signal line 207 and the address signal line 208, and the ROM 204 is connected with the readout control line 209 and the address signal line 210. Further, via the buffer section 228, the memory enable line 211 and the address line 212 are connected, which are used at test and given from the external terminal 235, and the address signal line 214 and the control signal line 213 are connected via the buffer section 229.
COPYRIGHT: (C)1980,JPO&Japio
JP13695678A 1978-11-07 1978-11-07 Integrated circuit Granted JPS5563432A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13695678A JPS5563432A (en) 1978-11-07 1978-11-07 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13695678A JPS5563432A (en) 1978-11-07 1978-11-07 Integrated circuit

Publications (2)

Publication Number Publication Date
JPS5563432A true JPS5563432A (en) 1980-05-13
JPS6211382B2 JPS6211382B2 (en) 1987-03-12

Family

ID=15187426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13695678A Granted JPS5563432A (en) 1978-11-07 1978-11-07 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS5563432A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57123455A (en) * 1981-01-23 1982-07-31 Nec Corp Instruction executing device
JPS6085500A (en) * 1983-10-18 1985-05-14 Fujitsu Ltd Test method for memory with built-in highly integrated circuit elements
JPS60193056A (en) * 1984-03-14 1985-10-01 Nec Corp Single chip microcomputer
JPS61128343A (en) * 1984-11-28 1986-06-16 Nec Corp Microcomputer device
JPS63311458A (en) * 1987-06-12 1988-12-20 Fujitsu Ltd Memory testing system for information processor
US6449740B1 (en) 1998-08-05 2002-09-10 Nec Corporation Conductive paths controllably coupling pad groups arranged along one edge to CPU and to EEPROM in test mode

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50115742A (en) * 1974-02-21 1975-09-10
JPS52138849A (en) * 1976-05-14 1977-11-19 Nec Corp Logic integrated circuit
JPS5324285A (en) * 1976-08-18 1978-03-06 Matsushita Electric Ind Co Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50115742A (en) * 1974-02-21 1975-09-10
JPS52138849A (en) * 1976-05-14 1977-11-19 Nec Corp Logic integrated circuit
JPS5324285A (en) * 1976-08-18 1978-03-06 Matsushita Electric Ind Co Ltd Semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57123455A (en) * 1981-01-23 1982-07-31 Nec Corp Instruction executing device
JPH0157824B2 (en) * 1981-01-23 1989-12-07 Nippon Electric Co
JPS6085500A (en) * 1983-10-18 1985-05-14 Fujitsu Ltd Test method for memory with built-in highly integrated circuit elements
JPS60193056A (en) * 1984-03-14 1985-10-01 Nec Corp Single chip microcomputer
JPS61128343A (en) * 1984-11-28 1986-06-16 Nec Corp Microcomputer device
JPH0465409B2 (en) * 1984-11-28 1992-10-20 Nippon Electric Co
JPS63311458A (en) * 1987-06-12 1988-12-20 Fujitsu Ltd Memory testing system for information processor
US6449740B1 (en) 1998-08-05 2002-09-10 Nec Corporation Conductive paths controllably coupling pad groups arranged along one edge to CPU and to EEPROM in test mode

Also Published As

Publication number Publication date
JPS6211382B2 (en) 1987-03-12

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