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JPS55115155A - One chip multi-microcomputer - Google Patents

One chip multi-microcomputer

Info

Publication number
JPS55115155A
JPS55115155A JP2225279A JP2225279A JPS55115155A JP S55115155 A JPS55115155 A JP S55115155A JP 2225279 A JP2225279 A JP 2225279A JP 2225279 A JP2225279 A JP 2225279A JP S55115155 A JPS55115155 A JP S55115155A
Authority
JP
Japan
Prior art keywords
instruction
address
program
memory
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2225279A
Other languages
Japanese (ja)
Inventor
Takashi Sakao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2225279A priority Critical patent/JPS55115155A/en
Publication of JPS55115155A publication Critical patent/JPS55115155A/en
Pending legal-status Critical Current

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  • Microcomputers (AREA)

Abstract

PURPOSE: To constitute one chip multi-microcomputer simply on the semiconductor integrated circuit, by selecting a plurality sets of program status, enabling to execute a plurality of programs in the instruction memory.
CONSTITUTION: A plurality sets of program status PS1A, 1B respectively containing the stack pointer indicating the stack address, program counter indicating the address of executive instruction, internal flag including the operation flag in the control system and exclusive use register including the address register of the data memory 6, are provided. Further, the instruction memory 2 storing the progtam, instruction decoder 4 producing the control signal from the instruction word, data memory 6, arithmetic logical operation section 7, input and output circuit 8, internal data bus 9, PS selection circuit 10, and PS selection control circuit 11, are provided and one chip microcomputer is constituted so that control program is alternately executed by one instruction with the circuits 11 and 10 for PS1A, 1B.
COPYRIGHT: (C)1980,JPO&Japio
JP2225279A 1979-02-27 1979-02-27 One chip multi-microcomputer Pending JPS55115155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2225279A JPS55115155A (en) 1979-02-27 1979-02-27 One chip multi-microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2225279A JPS55115155A (en) 1979-02-27 1979-02-27 One chip multi-microcomputer

Publications (1)

Publication Number Publication Date
JPS55115155A true JPS55115155A (en) 1980-09-04

Family

ID=12077588

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2225279A Pending JPS55115155A (en) 1979-02-27 1979-02-27 One chip multi-microcomputer

Country Status (1)

Country Link
JP (1) JPS55115155A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56164442A (en) * 1980-05-22 1981-12-17 Fujitsu Ltd Response system between microprogram processing devices
JPS63311477A (en) * 1987-06-13 1988-12-20 Fujitsu Ten Ltd Method and device for arithmetic operation
JPH06223045A (en) * 1983-05-31 1994-08-12 Daburiyuu Danieru Hirisu Parallel processor
US7386707B2 (en) 2002-01-09 2008-06-10 Matsushita Electric Industrial Co., Ltd. Processor and program execution method capable of efficient program execution
US7735087B2 (en) 2003-03-13 2010-06-08 Panasonic Corporation Task switching apparatus, method and program

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56164442A (en) * 1980-05-22 1981-12-17 Fujitsu Ltd Response system between microprogram processing devices
JPH06223045A (en) * 1983-05-31 1994-08-12 Daburiyuu Danieru Hirisu Parallel processor
JPS63311477A (en) * 1987-06-13 1988-12-20 Fujitsu Ten Ltd Method and device for arithmetic operation
US7386707B2 (en) 2002-01-09 2008-06-10 Matsushita Electric Industrial Co., Ltd. Processor and program execution method capable of efficient program execution
US7921281B2 (en) 2002-01-09 2011-04-05 Panasonic Corporation Processor and program execution method capable of efficient program execution
US7930520B2 (en) 2002-01-09 2011-04-19 Panasonic Corporation Processor and program execution method capable of efficient program execution
US8006076B2 (en) 2002-01-09 2011-08-23 Panasonic Corporation Processor and program execution method capable of efficient program execution
US8719827B2 (en) 2002-01-09 2014-05-06 Panasonic Corporation Processor and program execution method capable of efficient program execution
US9823946B2 (en) 2002-01-09 2017-11-21 Socionext Inc. Processor and program execution method capable of efficient program execution
US7735087B2 (en) 2003-03-13 2010-06-08 Panasonic Corporation Task switching apparatus, method and program
US7950016B2 (en) 2003-03-13 2011-05-24 Panasonic Corporation Apparatus for switching the task to be completed in a processor by switching to the task assigned time slot
US8276156B2 (en) 2003-03-13 2012-09-25 Panasonic Corporation Task switching based on assigned time slot

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