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JPS55159226A - Data input and output unit - Google Patents

Data input and output unit

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Publication number
JPS55159226A
JPS55159226A JP6914279A JP6914279A JPS55159226A JP S55159226 A JPS55159226 A JP S55159226A JP 6914279 A JP6914279 A JP 6914279A JP 6914279 A JP6914279 A JP 6914279A JP S55159226 A JPS55159226 A JP S55159226A
Authority
JP
Japan
Prior art keywords
input
data
output interface
control circuit
output unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6914279A
Other languages
Japanese (ja)
Inventor
Fumio Yamano
Tetsuo Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6914279A priority Critical patent/JPS55159226A/en
Publication of JPS55159226A publication Critical patent/JPS55159226A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To increase the memory efficiency of central processing unit (CPU), by providing the input and output interface and the control circuit.
CONSTITUTION: The data input and output unit provides a CPU5, memories 6 and 7, a input and output circuit 8, a input and output interface 19 and a control circuit 20. The input and output interface 19 has a register 21 temporarily storing the data transferred and a status flip-flop 22 representing the status of the data set in the register 21. Further, a pointer 23 producing the address to read out the data transferred, counter 24 to designate the number of transferred data and a transfer control circuit 25 are provided. Thus, the transfer of data can directly be accessed and the memory efficiency can be increased for CPU with the provision of the input and output interface.
COPYRIGHT: (C)1980,JPO&Japio
JP6914279A 1979-05-30 1979-05-30 Data input and output unit Pending JPS55159226A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6914279A JPS55159226A (en) 1979-05-30 1979-05-30 Data input and output unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6914279A JPS55159226A (en) 1979-05-30 1979-05-30 Data input and output unit

Publications (1)

Publication Number Publication Date
JPS55159226A true JPS55159226A (en) 1980-12-11

Family

ID=13394094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6914279A Pending JPS55159226A (en) 1979-05-30 1979-05-30 Data input and output unit

Country Status (1)

Country Link
JP (1) JPS55159226A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57120144A (en) * 1981-01-16 1982-07-27 Toshiba Corp Data transfer system
JPH05233894A (en) * 1983-10-08 1993-09-10 Dainippon Printing Co Ltd Method and device for processing ic card and ic card

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57120144A (en) * 1981-01-16 1982-07-27 Toshiba Corp Data transfer system
JPH05233894A (en) * 1983-10-08 1993-09-10 Dainippon Printing Co Ltd Method and device for processing ic card and ic card

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