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JPS54122059A - Inter-processor information transfer system - Google Patents

Inter-processor information transfer system

Info

Publication number
JPS54122059A
JPS54122059A JP3016978A JP3016978A JPS54122059A JP S54122059 A JPS54122059 A JP S54122059A JP 3016978 A JP3016978 A JP 3016978A JP 3016978 A JP3016978 A JP 3016978A JP S54122059 A JPS54122059 A JP S54122059A
Authority
JP
Japan
Prior art keywords
processor
control circuit
information
transfer
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3016978A
Other languages
Japanese (ja)
Inventor
Kazunori Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3016978A priority Critical patent/JPS54122059A/en
Priority to US05/917,342 priority patent/US4210782A/en
Publication of JPS54122059A publication Critical patent/JPS54122059A/en
Pending legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

PURPOSE: To obtain an inter-processor information transfer system which makes it possible to reduce the memory capacity, by simplifying the constitution of a program to be executed by processors among which the information transfer is required.
CONSTITUTION: To transfer information from processor 11 to processor 12, processor 11 sends address information, in a transfer information memory area provided to the specific address of temporarily-memory control circuit 31, to control circuit 31 via address bus 41 and also sends data, written into the transfer information memory area, to control circuit 31 via data bus 51. The data written in the specific address of this control circuit 31 are read out and then stored in the transfer information memory area of temporarily-memory control circuit 32 via inter-processor information transfer bus 6. Processor 12 sends out address information for reading out contents stored in the specific address of control circuit 32 via address bus 42 and then, the data stored are sent back to processor 12 via data bus 52.
COPYRIGHT: (C)1979,JPO&Japio
JP3016978A 1977-06-23 1978-03-15 Inter-processor information transfer system Pending JPS54122059A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP3016978A JPS54122059A (en) 1978-03-15 1978-03-15 Inter-processor information transfer system
US05/917,342 US4210782A (en) 1977-06-23 1978-06-20 Distributed control type telephone switching system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3016978A JPS54122059A (en) 1978-03-15 1978-03-15 Inter-processor information transfer system

Publications (1)

Publication Number Publication Date
JPS54122059A true JPS54122059A (en) 1979-09-21

Family

ID=12296242

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3016978A Pending JPS54122059A (en) 1977-06-23 1978-03-15 Inter-processor information transfer system

Country Status (1)

Country Link
JP (1) JPS54122059A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60130995A (en) * 1983-12-19 1985-07-12 Nippon Telegr & Teleph Corp <Ntt> Inter-processor communication control method
JPS60130994A (en) * 1983-12-19 1985-07-12 Nippon Telegr & Teleph Corp <Ntt> Communication system between processors
JPS61856A (en) * 1984-03-10 1986-01-06 ゴールド・インコーポレーテッド Real time data processor
JPS6232748A (en) * 1985-08-05 1987-02-12 Mitsubishi Electric Corp Data transfer equipment
WO1988009017A1 (en) * 1987-05-06 1988-11-17 Fujitsu Ten Limited Method and apparatus for data transfer
JPS63311466A (en) * 1987-06-13 1988-12-20 Fujitsu Ten Ltd Write or read system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5017741A (en) * 1973-06-18 1975-02-25
JPS5215242A (en) * 1975-07-28 1977-02-04 Nec Corp Mutual communication system among processors

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5017741A (en) * 1973-06-18 1975-02-25
JPS5215242A (en) * 1975-07-28 1977-02-04 Nec Corp Mutual communication system among processors

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60130995A (en) * 1983-12-19 1985-07-12 Nippon Telegr & Teleph Corp <Ntt> Inter-processor communication control method
JPS60130994A (en) * 1983-12-19 1985-07-12 Nippon Telegr & Teleph Corp <Ntt> Communication system between processors
JPS61856A (en) * 1984-03-10 1986-01-06 ゴールド・インコーポレーテッド Real time data processor
JPS6232748A (en) * 1985-08-05 1987-02-12 Mitsubishi Electric Corp Data transfer equipment
WO1988009017A1 (en) * 1987-05-06 1988-11-17 Fujitsu Ten Limited Method and apparatus for data transfer
JPS63311466A (en) * 1987-06-13 1988-12-20 Fujitsu Ten Ltd Write or read system

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