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JPS5660953A - Control storage device - Google Patents

Control storage device

Info

Publication number
JPS5660953A
JPS5660953A JP13634179A JP13634179A JPS5660953A JP S5660953 A JPS5660953 A JP S5660953A JP 13634179 A JP13634179 A JP 13634179A JP 13634179 A JP13634179 A JP 13634179A JP S5660953 A JPS5660953 A JP S5660953A
Authority
JP
Japan
Prior art keywords
microprogram
bus
cpu1
storage device
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13634179A
Other languages
Japanese (ja)
Inventor
Makoto Noda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13634179A priority Critical patent/JPS5660953A/en
Publication of JPS5660953A publication Critical patent/JPS5660953A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To simplify the constitution of the address bus of an electronic computer on the microprogram control system by arranging a microprogram and user program in memory areas of the same storage device.
CONSTITUTION: A microprogram and user program are stored in microprogram area 4 and user program area 3 of storage device 2. From CPU1, the contents of program counter 6 are sent to device 2 via address bus 5 and user instructions are accessed and fetched by CPU1 via data bus 7. The contents of the starting address of the microprogram for executing fetched user instructions are sent from CPU1 to bus 5 and microinstructions in device 2 are addressed. Microinstructions read out of area 3 are sent to CPU1 via bus 7 and the microprogram is executed. Thus, the address bus can be made into one system and its constitution can be simplified.
COPYRIGHT: (C)1981,JPO&Japio
JP13634179A 1979-10-24 1979-10-24 Control storage device Pending JPS5660953A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13634179A JPS5660953A (en) 1979-10-24 1979-10-24 Control storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13634179A JPS5660953A (en) 1979-10-24 1979-10-24 Control storage device

Publications (1)

Publication Number Publication Date
JPS5660953A true JPS5660953A (en) 1981-05-26

Family

ID=15172930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13634179A Pending JPS5660953A (en) 1979-10-24 1979-10-24 Control storage device

Country Status (1)

Country Link
JP (1) JPS5660953A (en)

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