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JPS5481737A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5481737A
JPS5481737A JP15022677A JP15022677A JPS5481737A JP S5481737 A JPS5481737 A JP S5481737A JP 15022677 A JP15022677 A JP 15022677A JP 15022677 A JP15022677 A JP 15022677A JP S5481737 A JPS5481737 A JP S5481737A
Authority
JP
Japan
Prior art keywords
register
instruction
program
executing
microinstruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15022677A
Other languages
Japanese (ja)
Other versions
JPS6110856B2 (en
Inventor
Tetsuo Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15022677A priority Critical patent/JPS5481737A/en
Publication of JPS5481737A publication Critical patent/JPS5481737A/en
Publication of JPS6110856B2 publication Critical patent/JPS6110856B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To make dynamic for the utilization of program, by preparing the microprogram coded in advance on the main memory unit, designating the address on the memory unit of the program with the address section, and issuing the instruction mounting the program.
CONSTITUTION: The microprogram area 11 storing a plurality of microinstructions and the main memory unit 10 storing a plurality of microinstructions are provided, and when the instruction executing the microinstruction stored in the unit 10 is given from external, the content of the operand register 2 is fed to the address register 7, starting the interface control circuit 9 and the data are read out from the unit 10 and inputted to the microcommand register 15, executing the microinstruction. Further, if the execution instruction is not given, the microprogram area generation circuit 4 is operated with the result of interpretation of the operation code register through the decoder 3, and the microinstruction of the area 11 is inputted to the register 15, executing the instruction.
COPYRIGHT: (C)1979,JPO&Japio
JP15022677A 1977-12-13 1977-12-13 Information processor Granted JPS5481737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15022677A JPS5481737A (en) 1977-12-13 1977-12-13 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15022677A JPS5481737A (en) 1977-12-13 1977-12-13 Information processor

Publications (2)

Publication Number Publication Date
JPS5481737A true JPS5481737A (en) 1979-06-29
JPS6110856B2 JPS6110856B2 (en) 1986-03-31

Family

ID=15492290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15022677A Granted JPS5481737A (en) 1977-12-13 1977-12-13 Information processor

Country Status (1)

Country Link
JP (1) JPS5481737A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0430057Y2 (en) * 1986-05-28 1992-07-21
JPH0428782Y2 (en) * 1986-05-30 1992-07-13
JPH04111460U (en) * 1991-03-18 1992-09-28 フジコピアン株式会社 ink ribbon cassette

Also Published As

Publication number Publication date
JPS6110856B2 (en) 1986-03-31

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