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JPS56145432A - Microprocessor - Google Patents

Microprocessor

Info

Publication number
JPS56145432A
JPS56145432A JP4762280A JP4762280A JPS56145432A JP S56145432 A JPS56145432 A JP S56145432A JP 4762280 A JP4762280 A JP 4762280A JP 4762280 A JP4762280 A JP 4762280A JP S56145432 A JPS56145432 A JP S56145432A
Authority
JP
Japan
Prior art keywords
memory
processor
jump
register
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4762280A
Other languages
Japanese (ja)
Inventor
Takuro Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4762280A priority Critical patent/JPS56145432A/en
Publication of JPS56145432A publication Critical patent/JPS56145432A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Retry When Errors Occur (AREA)

Abstract

PURPOSE:To control an address in the start of a processor without any restriction upon software, by providing a three-bit shift register which operates with a memory read signal and a selecting circuit which selects one word among inputs to the register and by adding a simple circuit. CONSTITUTION:The microprocessor consists of microprocessor part 1, and memory 4 stored with a program controlling processor part 1. Further, three-bit capacity shift register 2 is provided which has a RESET signal terminal and performs shift operation in response to a readout timing signal from processor part 1 to memory 4. Then, an external jump instruction, a jump-destination address, and the readout output of memory 4 are applied to selecting circuit 3 via signal lines X1-X3 and X4 to select one of the jump instruction, jump-destination address and memory output according to the 1st-3rd bit outputs of register 2; and it is supplied to processor part 1 to control the address of the processor in its start.
JP4762280A 1980-04-11 1980-04-11 Microprocessor Pending JPS56145432A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4762280A JPS56145432A (en) 1980-04-11 1980-04-11 Microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4762280A JPS56145432A (en) 1980-04-11 1980-04-11 Microprocessor

Publications (1)

Publication Number Publication Date
JPS56145432A true JPS56145432A (en) 1981-11-12

Family

ID=12780303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4762280A Pending JPS56145432A (en) 1980-04-11 1980-04-11 Microprocessor

Country Status (1)

Country Link
JP (1) JPS56145432A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60108924A (en) * 1983-10-18 1985-06-14 オートモビル　シトロエン Improved electric energy distributor having microprocessor
JPS6234217A (en) * 1985-08-06 1987-02-14 Sharp Corp Sentence processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60108924A (en) * 1983-10-18 1985-06-14 オートモビル　シトロエン Improved electric energy distributor having microprocessor
JPS6234217A (en) * 1985-08-06 1987-02-14 Sharp Corp Sentence processor

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