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JPS55129837A - Microprogram address control unit - Google Patents

Microprogram address control unit

Info

Publication number
JPS55129837A
JPS55129837A JP3557579A JP3557579A JPS55129837A JP S55129837 A JPS55129837 A JP S55129837A JP 3557579 A JP3557579 A JP 3557579A JP 3557579 A JP3557579 A JP 3557579A JP S55129837 A JPS55129837 A JP S55129837A
Authority
JP
Japan
Prior art keywords
register
address
microprogram
circuit
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3557579A
Other languages
Japanese (ja)
Other versions
JPS6122816B2 (en
Inventor
Hideo Maejima
Hidekazu Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3557579A priority Critical patent/JPS55129837A/en
Publication of JPS55129837A publication Critical patent/JPS55129837A/en
Publication of JPS6122816B2 publication Critical patent/JPS6122816B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the number of pins of LSI by giving flexibility, by the entry of the output from the memory circuit and the microprogram address forming circuit to the microprogram address register for suitable synthesis.
CONSTITUTION: In the unit synthesizing partial data of the micro-instruction in the address designation field and the output of the microprogram address forming circuit 106, the micro instruction read out from the microprogram memory 101 is entered to the micro instruction register 103 or address register 104. On the other hand, the instruction read out from the main memory 102 is entered to the instruction register 105 and entered to the register 104 with the circuit 106. Thus, the register 104 gives entry for the data from the circuit 106 and the memory 101, and these are suitably synthesized to form one address, enabling to reduce the number of pins of LSI with flexibility.
COPYRIGHT: (C)1980,JPO&Japio
JP3557579A 1979-03-28 1979-03-28 Microprogram address control unit Granted JPS55129837A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3557579A JPS55129837A (en) 1979-03-28 1979-03-28 Microprogram address control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3557579A JPS55129837A (en) 1979-03-28 1979-03-28 Microprogram address control unit

Publications (2)

Publication Number Publication Date
JPS55129837A true JPS55129837A (en) 1980-10-08
JPS6122816B2 JPS6122816B2 (en) 1986-06-03

Family

ID=12445551

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3557579A Granted JPS55129837A (en) 1979-03-28 1979-03-28 Microprogram address control unit

Country Status (1)

Country Link
JP (1) JPS55129837A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57203141A (en) * 1981-06-10 1982-12-13 Hitachi Ltd Method and device for controlling microprogram
JPS61101837A (en) * 1984-10-24 1986-05-20 Nippon Telegr & Teleph Corp <Ntt> Arithmetic unit
JPH0367333A (en) * 1981-04-13 1991-03-22 Texas Instr Inc <Ti> Microprocessor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0367333A (en) * 1981-04-13 1991-03-22 Texas Instr Inc <Ti> Microprocessor device
JPS57203141A (en) * 1981-06-10 1982-12-13 Hitachi Ltd Method and device for controlling microprogram
JPS61101837A (en) * 1984-10-24 1986-05-20 Nippon Telegr & Teleph Corp <Ntt> Arithmetic unit
JPH0310974B2 (en) * 1984-10-24 1991-02-14 Nippon Telegraph & Telephone

Also Published As

Publication number Publication date
JPS6122816B2 (en) 1986-06-03

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