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JPS5591055A - Information process system - Google Patents

Information process system

Info

Publication number
JPS5591055A
JPS5591055A JP16238878A JP16238878A JPS5591055A JP S5591055 A JPS5591055 A JP S5591055A JP 16238878 A JP16238878 A JP 16238878A JP 16238878 A JP16238878 A JP 16238878A JP S5591055 A JPS5591055 A JP S5591055A
Authority
JP
Japan
Prior art keywords
memory
order
case
output
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16238878A
Other languages
Japanese (ja)
Inventor
Hiroshi Ichii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16238878A priority Critical patent/JPS5591055A/en
Publication of JPS5591055A publication Critical patent/JPS5591055A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To decrease the hardware quantity of the information process system by making common the microprogram control memory and then securing the time- division use of the common memory device for each of plural units of information processors.
CONSTITUTION: Input/output control units 1 and 2 are provided, and the microprogram which can be used in common to both units 1 and 2 is stored in control memory 3. And in case the order read out of memory 3 by order decoder 4 is the branch order, the indication is given to multiplexer 6 to select and deliver the branch addresses. While in the case of the non-branch order, the command is given to select the output of +1 circuit 23-1 and 23-2, and the output of multiolexer 6 is set to address registers 7-1 and 7-2 each. In addition, multiplexer 8 selects register 7-1 in case the address selection signal is 1, and then selects register 7-2 in the case of 0 respectively. And the selection output is applied to memory 3, and the order is read out of memory 3. Then the control and arithmetic control fields are supplied to arithmetic process parts 5-1 and 5-2 in the time-division way.
COPYRIGHT: (C)1980,JPO&Japio
JP16238878A 1978-12-29 1978-12-29 Information process system Pending JPS5591055A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16238878A JPS5591055A (en) 1978-12-29 1978-12-29 Information process system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16238878A JPS5591055A (en) 1978-12-29 1978-12-29 Information process system

Publications (1)

Publication Number Publication Date
JPS5591055A true JPS5591055A (en) 1980-07-10

Family

ID=15753625

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16238878A Pending JPS5591055A (en) 1978-12-29 1978-12-29 Information process system

Country Status (1)

Country Link
JP (1) JPS5591055A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6324349A (en) * 1986-07-16 1988-02-01 Kokusai Electric Co Ltd memory access device
JPH0393312A (en) * 1989-09-06 1991-04-18 Yagi Antenna Co Ltd PLL digital synthesizer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6324349A (en) * 1986-07-16 1988-02-01 Kokusai Electric Co Ltd memory access device
JPH0393312A (en) * 1989-09-06 1991-04-18 Yagi Antenna Co Ltd PLL digital synthesizer

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