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JPS5599653A - Microprogram control system - Google Patents

Microprogram control system

Info

Publication number
JPS5599653A
JPS5599653A JP686779A JP686779A JPS5599653A JP S5599653 A JPS5599653 A JP S5599653A JP 686779 A JP686779 A JP 686779A JP 686779 A JP686779 A JP 686779A JP S5599653 A JPS5599653 A JP S5599653A
Authority
JP
Japan
Prior art keywords
microorder
rom4
selector
execution
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP686779A
Other languages
Japanese (ja)
Inventor
Toshio Iwao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP686779A priority Critical patent/JPS5599653A/en
Publication of JPS5599653A publication Critical patent/JPS5599653A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase the processing speed for execution of the user order by securing the simultaneous selection for both contents of the main memory means and the map memory means.
CONSTITUTION: The operation code part of the user order designates simultaneously the address of both map read-only memory MAPROM2 and main memory ROM4, and then transfers the data of the designated address in MAPROM2 to selector 7 and the microorder of the designated address in ROM4 to decoder 6 and selector 7 each in order to process the user order. In case the processing is impossible with one microorder, +1 is given to ROM address register 5 via the microorder read out of ROM4 via selector 7 and by the output of decoder 6 to read out the microorder of ROM4 until the second execution process completes with every execution of the microorder. As a result, ROM4 can be designated directly through the operation code part of the user.
COPYRIGHT: (C)1980,JPO&Japio
JP686779A 1979-01-24 1979-01-24 Microprogram control system Pending JPS5599653A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP686779A JPS5599653A (en) 1979-01-24 1979-01-24 Microprogram control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP686779A JPS5599653A (en) 1979-01-24 1979-01-24 Microprogram control system

Publications (1)

Publication Number Publication Date
JPS5599653A true JPS5599653A (en) 1980-07-29

Family

ID=11650181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP686779A Pending JPS5599653A (en) 1979-01-24 1979-01-24 Microprogram control system

Country Status (1)

Country Link
JP (1) JPS5599653A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6375833A (en) * 1986-09-18 1988-04-06 Toshiba Corp Information processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6375833A (en) * 1986-09-18 1988-04-06 Toshiba Corp Information processor

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