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JPS55166747A - Data processor - Google Patents

Data processor

Info

Publication number
JPS55166747A
JPS55166747A JP7580579A JP7580579A JPS55166747A JP S55166747 A JPS55166747 A JP S55166747A JP 7580579 A JP7580579 A JP 7580579A JP 7580579 A JP7580579 A JP 7580579A JP S55166747 A JPS55166747 A JP S55166747A
Authority
JP
Japan
Prior art keywords
contents
register
memory unit
circuit
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7580579A
Other languages
Japanese (ja)
Other versions
JPS6155698B2 (en
Inventor
Takao Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7580579A priority Critical patent/JPS55166747A/en
Publication of JPS55166747A publication Critical patent/JPS55166747A/en
Publication of JPS6155698B2 publication Critical patent/JPS6155698B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE: To make it possible to cope with a fault in read operation by making use of the doubling of the same data, by making it possible to write the same data in different memory areas or in another memory unit at the same time through one instruction operation.
CONSTITUTION: According to the contents of base address register assignment register 102, selecting circuit 107 selects base address register 104, contents (n) of which are sent to adding circuit 108. Adding circuit 108 adds contents (m) of address register 103 to output (n) of selecting circuit 107 and sum m+n is sent to gate circuit 110 to generate an address as to memory unit 111. According to the contents of operation assignment register 101, both or either of gate circuits 109 and 110 is brought under control to write data in memory unit 111. An address in read operation is similarly generated as mentioned above.
COPYRIGHT: (C)1980,JPO&Japio
JP7580579A 1979-06-15 1979-06-15 Data processor Granted JPS55166747A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7580579A JPS55166747A (en) 1979-06-15 1979-06-15 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7580579A JPS55166747A (en) 1979-06-15 1979-06-15 Data processor

Publications (2)

Publication Number Publication Date
JPS55166747A true JPS55166747A (en) 1980-12-26
JPS6155698B2 JPS6155698B2 (en) 1986-11-28

Family

ID=13586771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7580579A Granted JPS55166747A (en) 1979-06-15 1979-06-15 Data processor

Country Status (1)

Country Link
JP (1) JPS55166747A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02301831A (en) * 1989-05-17 1990-12-13 Mitsubishi Electric Corp Digital signal processor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0337831Y2 (en) * 1986-04-21 1991-08-09

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02301831A (en) * 1989-05-17 1990-12-13 Mitsubishi Electric Corp Digital signal processor

Also Published As

Publication number Publication date
JPS6155698B2 (en) 1986-11-28

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