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JPH0481063U - - Google Patents

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Publication number
JPH0481063U
JPH0481063U JP12434490U JP12434490U JPH0481063U JP H0481063 U JPH0481063 U JP H0481063U JP 12434490 U JP12434490 U JP 12434490U JP 12434490 U JP12434490 U JP 12434490U JP H0481063 U JPH0481063 U JP H0481063U
Authority
JP
Japan
Prior art keywords
pulse
circuit
input
period
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12434490U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12434490U priority Critical patent/JPH0481063U/ja
Publication of JPH0481063U publication Critical patent/JPH0481063U/ja
Pending legal-status Critical Current

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Landscapes

  • Manipulation Of Pulses (AREA)
  • Measuring Phase Differences (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例の四倍周回路を用い
たパルス入力ブロツク図、第2図は本考案の実施
例である四倍周回路図、第3図および第4図は本
考案による四倍周回路を用いたパルス入力回路に
おけるパルスカウントの動作図、第5図は従来の
パルス入力ブロツク図、第6図および第7図は従
来のパルス入力回路におけるパルスカウントの動
作図である。 5……四倍周回路、6……位相回路(90°遅
れ)、7,8……反転器、10……パルス変換回
路、T……パルス数測定時間、f……入力周波数
Fig. 1 is a pulse input block diagram using a quadruple frequency circuit according to an embodiment of the present invention, Fig. 2 is a quadruple frequency circuit diagram according to an embodiment of the present invention, and Figs. 3 and 4 are diagrams according to the present invention. Figure 5 is a conventional pulse input block diagram, and Figures 6 and 7 are diagrams of pulse counting operation in a conventional pulse input circuit. . 5... Quadruple frequency circuit, 6... Phase circuit (90° delay), 7, 8... Inverter, 10... Pulse conversion circuit, T... Pulse number measurement time, f... Input frequency.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の位相回路を有する倍周回路を用いる事に
より、入力パルスの一周期以下のパルスカウント
を可能とすることを特徴とするパルス入力回路。
A pulse input circuit characterized in that it is possible to count pulses of one period or less of an input pulse by using a frequency doubler circuit having a plurality of phase circuits.
JP12434490U 1990-11-28 1990-11-28 Pending JPH0481063U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12434490U JPH0481063U (en) 1990-11-28 1990-11-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12434490U JPH0481063U (en) 1990-11-28 1990-11-28

Publications (1)

Publication Number Publication Date
JPH0481063U true JPH0481063U (en) 1992-07-15

Family

ID=31872002

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12434490U Pending JPH0481063U (en) 1990-11-28 1990-11-28

Country Status (1)

Country Link
JP (1) JPH0481063U (en)

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