JPH0480138U - - Google Patents
Info
- Publication number
- JPH0480138U JPH0480138U JP12357290U JP12357290U JPH0480138U JP H0480138 U JPH0480138 U JP H0480138U JP 12357290 U JP12357290 U JP 12357290U JP 12357290 U JP12357290 U JP 12357290U JP H0480138 U JPH0480138 U JP H0480138U
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- period
- signal
- clock
- counter means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Feedback Control In General (AREA)
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案に係るＤ／Ａ変換装置の一実施
例を示すブロツク図、第２図は従来のＤ／Ａ変換
装置のブロツク図、第３図は第２図のＤ／Ａ変換
装置の動作を説明する波形図である。
１……クロツク出力回路、３，１３，２３……
ＡＮＤ回路、５……カウンタ回路、７……ラツチ
回路、９……Ｄ／Ａ変換回路、１１，４３……コ
ントロール回路、１５……第１のクロツク出力手
段（第１のクロツク出力回路）、１７……第１の
カウンタ回路、１９……第１のラツチ回路、２１
……第１のカウンタ手段、２５……第２のカウン
タ回路、２７……第２のラツチ回路、２９……第
２のカウンタ手段、３１……第２のクロツク出力
手段（第２のクロツク出力回路）、３３……第３
のカウンタ回路、３５……第４のカウンタ回路、
３７……切換回路、３９……第２のＰＷＭ信号発
生手段、４１……Ｄ／Ａ変換手段（Ｄ／Ａ変換回
路）。
Fig. 1 is a block diagram showing an embodiment of the D/A converter according to the present invention, Fig. 2 is a block diagram of a conventional D/A converter, and Fig. 3 is the D/A converter shown in Fig. 2. FIG. 2 is a waveform diagram illustrating the operation of FIG. 1...Clock output circuit, 3, 13, 23...
AND circuit, 5... Counter circuit, 7... Latch circuit, 9... D/A conversion circuit, 11, 43... Control circuit, 15... First clock output means (first clock output circuit), 17...first counter circuit, 19...first latch circuit, 21
...first counter means, 25 ... second counter circuit, 27 ... second latch circuit, 29 ... second counter means, 31 ... second clock output means (second clock output circuit), 33...3rd
counter circuit, 35... fourth counter circuit,
37...Switching circuit, 39...Second PWM signal generation means, 41...D/A conversion means (D/A conversion circuit).
Claims (1)
出力手段と、 前記第１のクロツク信号より高い周波数の第２
のクロツク信号を出力する第２のクロツク出力手
段と、 入力された第１のＰＷＭ信号のＯＮ期間を前記
第１のクロツク信号でカウントする第１のカウン
タ手段と、 前記第１のＰＷＭ信号のＯＦＦ期間を前記第１
のクロツク信号でカウントする第２のカウンタ手
段と、 前記第１のカウンタ手段によるカウント値を前
記第２のクロツク信号でカウントする期間をＯＮ
期間とするとともに、前記第２のカウンタ手段に
よるカウント値を前記第２のクロツク信号でカウ
ントする期間をＯＦＦ期間とした第２のＰＷＭ信
号を発生する第２のＰＷＭ信号発生手段と、 前記第２のＰＷＭ信号をＤ／Ａ変換してアナロ
グ化するＤ／Ａ変換手段と、 を具備することを特徴とするＤ／Ａ変換装置。[Claims for Utility Model Registration] A first clock output means for outputting a first clock signal, and a second clock signal having a higher frequency than the first clock signal.
a second clock output means for outputting a clock signal; a first counter means for counting the ON period of the inputted first PWM signal using the first clock signal; and a first counter means for counting the ON period of the input first PWM signal; Set the period to the first
a second counter means that counts using the clock signal; and a period during which the count value of the first counter means is counted using the second clock signal.
a second PWM signal generating means for generating a second PWM signal whose OFF period is a period in which the count value by the second counter means is counted by the second clock signal; A D/A conversion device, comprising: D/A conversion means for D/A converting a PWM signal into an analog signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990123572U JP2517764Y2 (en) | 1990-11-27 | 1990-11-27 | D / A converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990123572U JP2517764Y2 (en) | 1990-11-27 | 1990-11-27 | D / A converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0480138U true JPH0480138U (en) | 1992-07-13 |
| JP2517764Y2 JP2517764Y2 (en) | 1996-11-20 |
Family
ID=31871268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990123572U Expired - Fee Related JP2517764Y2 (en) | 1990-11-27 | 1990-11-27 | D / A converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2517764Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58101518A (en) * | 1981-12-14 | 1983-06-16 | Toshiba Corp | Analog-to-digital converter |
| JPS63146492U (en) * | 1987-03-17 | 1988-09-27 |
-
1990
- 1990-11-27 JP JP1990123572U patent/JP2517764Y2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58101518A (en) * | 1981-12-14 | 1983-06-16 | Toshiba Corp | Analog-to-digital converter |
| JPS63146492U (en) * | 1987-03-17 | 1988-09-27 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2517764Y2 (en) | 1996-11-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS5877490U (en) | Clock electronic alarm sound generation circuit | |
| JPH0480138U (en) | ||
| JPH0481063U (en) | ||
| JPH0648434Y2 (en) | Voltage-pulse width converter | |
| JPS5950596U (en) | Pulse motor drive circuit | |
| JPS63171033U (en) | ||
| JPH0363868U (en) | ||
| JPS62198739U (en) | ||
| JPS62198738U (en) | ||
| JPS60158161U (en) | frequency/voltage converter | |
| JPH01169808U (en) | ||
| JPS6232430U (en) | ||
| JPH0353041U (en) | ||
| JPS62188845U (en) | ||
| JPS6183321U (en) | ||
| JPS6323830U (en) | ||
| JPS6387951U (en) | ||
| JPS5837702U (en) | Variable speed motor drive device for electric vehicles | |
| JPS63126872U (en) | ||
| JPH025938U (en) | ||
| JPS60142528U (en) | Intermittent frequency signal generation circuit | |
| JPH0366224U (en) | ||
| JPH03109435U (en) | ||
| JPS61154024U (en) | ||
| JPS6399277U (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |