JPS6197234U - - Google Patents
Info
- Publication number
- JPS6197234U JPS6197234U JP18189784U JP18189784U JPS6197234U JP S6197234 U JPS6197234 U JP S6197234U JP 18189784 U JP18189784 U JP 18189784U JP 18189784 U JP18189784 U JP 18189784U JP S6197234 U JPS6197234 U JP S6197234U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- clock
- generating
- feedback
- timing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図および第２図はそれぞれ、本考案による
帰還回路付き同期カウンタの一実施例を示す回路
図、およびその動作を示すタイムチヤートである
。第３図および第４図はそれぞれ、従来技術によ
る帰還回路付き同期カウンタの一例を示す回路図
、およびその動作を示すタイムチヤートである。
１〜６…フリツプフロツプ、１０，１１，１５
…ＡＮＤゲート、１２…ＯＲゲート、１３，１４
…インバータ。
1 and 2 are a circuit diagram showing an embodiment of a synchronous counter with a feedback circuit according to the present invention, and a time chart showing its operation, respectively. 3 and 4 are a circuit diagram showing an example of a synchronous counter with a feedback circuit according to the prior art, and a time chart showing its operation, respectively. 1-6...Flip-flop, 10, 11, 15
...AND gate, 12...OR gate, 13, 14
...Inverter.
Claims (1)
による同期カウント手段と、前記同期カウント手
段のリセツトパルスの発生するタイミングの1/2
クロツク前のタイミングで立上り、１クロツクの
幅を有する帰還パルスを生成するための帰還パル
ス生成手段と、前記帰還パルス、前記カウント定
段を構成する第１段目のフリツプロツプの出力の
負信号出力パルス、ならびにクロツクパルスの逆
相信号の３信号の論理積を取つてリセツトパルス
を生成するためのＡＮＤゲート手段とを具備して
構成したことを特徴とする帰還回路付き同期カウ
ンタ回路。 Synchronous counting means using edge trigger flip-flops connected in multiple stages, and 1/2 of the timing at which the reset pulse of the synchronous counting means is generated.
Feedback pulse generation means for generating a feedback pulse that rises at a timing before a clock and has a width of one clock, and the feedback pulse and a negative signal output pulse of the output of a first stage flip-flop constituting the counting fixed stage. , and AND gate means for generating a reset pulse by taking the logical product of three signals of reverse phase signals of a clock pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18189784U JPS6197234U (en) | 1984-11-30 | 1984-11-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18189784U JPS6197234U (en) | 1984-11-30 | 1984-11-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6197234U true JPS6197234U (en) | 1986-06-21 |
Family
ID=30739433
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18189784U Pending JPS6197234U (en) | 1984-11-30 | 1984-11-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6197234U (en) |
-
1984
- 1984-11-30 JP JP18189784U patent/JPS6197234U/ja active Pending
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