JPH0255740U - - Google Patents
Info
- Publication number
- JPH0255740U JPH0255740U JP13564888U JP13564888U JPH0255740U JP H0255740 U JPH0255740 U JP H0255740U JP 13564888 U JP13564888 U JP 13564888U JP 13564888 U JP13564888 U JP 13564888U JP H0255740 U JPH0255740 U JP H0255740U
- Authority
- JP
- Japan
- Prior art keywords
- synchronous
- synchronous counter
- flop
- flip
- counter device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 1
Landscapes
- Television Signal Processing For Recording (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図はこの考案に係る同期式カウンタ装置の
構成を示す回路図、第２図はドツトクロツクの分
周のタイミングを説明するタイムチヤート、第３
図はセツトパルスによる３分周のクロツクの発生
を説明するタイムチヤート、第４図はドツトクロ
ツクの入力からセツトパルスの発生までを説明す
るタイムチヤート、第５図はＰＬＬ発振器の構成
を示すブロツク図、第６図は従来の同期式カウン
タを多段接続した同期式カウンタ装置のブロツク
図である。
１４１ａ，ｂ，ｃ……カウンタ、１４２ｂ……
Ｄ―フリツプフロツプ、１４２ｃ……Ｄ―フリツ
プフロツプ。
Fig. 1 is a circuit diagram showing the configuration of the synchronous counter device according to this invention, Fig. 2 is a time chart explaining the timing of frequency division of the dot clock, and Fig.
The figure is a time chart explaining the generation of a 3-frequency clock by the set pulse, Figure 4 is a time chart explaining the process from the input of the dot clock to the generation of the set pulse, Figure 5 is a block diagram showing the configuration of the PLL oscillator, and Figure 6 The figure is a block diagram of a synchronous counter device in which conventional synchronous counters are connected in multiple stages. 141a, b, c...counter, 142b...
D-flipflop, 142c...D-flipflop.
Claims (1)
装置において、 最下段の同期式カウンタのクロツクを２分周す
るフリツプフロツプと、 該フリツプフロツプをセツトするか否かを切換
える切換手段と、 を備えることを特徴とする同期式カウンタ装置。[Scope of Claim for Utility Model Registration] A synchronous counter device in which synchronous counters are connected in multiple stages, comprising a flip-flop that divides the frequency of the lowest stage synchronous counter by two, and a switching means for switching whether or not to set the flip-flop. A synchronous counter device comprising: .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13564888U JPH0255740U (en) | 1988-10-18 | 1988-10-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13564888U JPH0255740U (en) | 1988-10-18 | 1988-10-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0255740U true JPH0255740U (en) | 1990-04-23 |
Family
ID=31395464
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13564888U Pending JPH0255740U (en) | 1988-10-18 | 1988-10-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0255740U (en) |
-
1988
- 1988-10-18 JP JP13564888U patent/JPH0255740U/ja active Pending