JPH0316734U - - Google Patents
Info
- Publication number
- JPH0316734U JPH0316734U JP7723189U JP7723189U JPH0316734U JP H0316734 U JPH0316734 U JP H0316734U JP 7723189 U JP7723189 U JP 7723189U JP 7723189 U JP7723189 U JP 7723189U JP H0316734 U JPH0316734 U JP H0316734U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- output
- frequency divider
- circuit
- rectangular wave
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案の好適な一実施例を示したブロ
ツク図、第２図は本考案の回路に入力される２種
類の信号を示した図、第３図乃至第５図は第２図
の入力信号に対して各ブロツクで出力されるタイ
ミング図である。
２，２′……オアゲート（論理和回路）、３…
…第１の分周器、４……発振器、５……第２の分
周器、６……アンドゲート（論理積回路）。
FIG. 1 is a block diagram showing a preferred embodiment of the present invention, FIG. 2 is a diagram showing two types of signals input to the circuit of the present invention, and FIGS. FIG. 3 is a timing diagram of output from each block in response to an input signal. 2, 2'...OR gate (logical sum circuit), 3...
...first frequency divider, 4...oscillator, 5...second frequency divider, 6...AND gate (AND circuit).
Claims (1)
任意時間の間ハイ、ローいずれか一方を保持して
出力される信号を入力し、前記任意時間の間には
周期的に変化する矩形波を出力し、任意時間の間
以外にはハイ、ローいずれか一方に保持された信
号を出力する回路であつて、少なくとも１つの発
振器と、前記発振器が出力する矩形波を計数しか
つ前記入力信号を入力し前記出力信号を出力する
第１の分周器と、前記発振器が出力する矩形波を
計数しかつ前記第１の分周器の出力信号を入力す
る第２の分周器と、この第２の分周器の出力信号
と前記発振器の矩形波信号との論理積をとる論理
積回路と、この論理積回路の出力信号と前記第１
の分周器に出力される入力信号との論理和をとる
第１の論理和回路と、この入力信号とこの第１の
分周器の出力信号との論理和をとる第２の論理和
回路から構成されることを特徴とする信号変換回
路。 Input a rectangular wave that changes periodically for an arbitrary time, or a signal that is output by holding either high or low for an arbitrary time, and output a rectangular wave that changes periodically during the arbitrary time. and a circuit that outputs a signal held at either high or low except during a given time, the circuit comprising at least one oscillator, counting the rectangular wave output from the oscillator, and inputting the input signal. a first frequency divider that outputs the output signal; a second frequency divider that counts the rectangular wave output from the oscillator and inputs the output signal of the first frequency divider; an AND circuit that ANDs the output signal of the frequency divider and the rectangular wave signal of the oscillator;
a first OR circuit that ORs the input signal output to the frequency divider; and a second OR circuit that ORs the input signal and the output signal of the first frequency divider. A signal conversion circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7723189U JPH0316734U (en) | 1989-06-30 | 1989-06-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7723189U JPH0316734U (en) | 1989-06-30 | 1989-06-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0316734U true JPH0316734U (en) | 1991-02-19 |
Family
ID=31619425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7723189U Pending JPH0316734U (en) | 1989-06-30 | 1989-06-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0316734U (en) |
-
1989
- 1989-06-30 JP JP7723189U patent/JPH0316734U/ja active Pending