JPS63121916U - - Google Patents
Info
- Publication number
- JPS63121916U JPS63121916U JP1150787U JP1150787U JPS63121916U JP S63121916 U JPS63121916 U JP S63121916U JP 1150787 U JP1150787 U JP 1150787U JP 1150787 U JP1150787 U JP 1150787U JP S63121916 U JPS63121916 U JP S63121916U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- exclusive
- delay
- output signal
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000284 extract Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図はこの考案に係るＮ倍周波数てい倍回路
の一実施例を示すブロツク図、第２図ａ〜第２図
ｇは第１図の各部の波形を示す図、第３図はこの
考案に係るＮ倍周波数てい倍回路の他の実施例を
示すブロツク図、第４図は従来のＮ倍周波数てい
倍回路を示すブロツク図である。
７……入力端子、８……パルス整形回路、９…
…第１遅延回路、１０……第２遅延回路、１１…
…第１排他的論理和回路、１２……第２排他的論
理和回路、１３……コンデンサ、１４……共振回
路、１５……出力端子、１６ａ〜１６ｎ……遅延
回路、１７ａ〜１７ｎ……排他的論理和回路。
Fig. 1 is a block diagram showing an embodiment of the N-times frequency multiplier circuit according to this invention, Figs. 2a to 2g are diagrams showing waveforms of each part of Fig. FIG. 4 is a block diagram showing a conventional N-times frequency multiplier circuit. 7...Input terminal, 8...Pulse shaping circuit, 9...
...First delay circuit, 10...Second delay circuit, 11...
...First exclusive OR circuit, 12...Second exclusive OR circuit, 13...Capacitor, 14...Resonance circuit, 15...Output terminal, 16a-16n...Delay circuit, 17a-17n... Exclusive OR circuit.
Claims (1)
を持つ第１遅延回路からＴ／２Ｎのステツプで遅
延時間の異なるＮ−１個の第２遅延回路〜第Ｎ−
１遅延回路と、入力信号と第１遅延回路の出力信
号との排他的論理和をとる第１排他的論理和回路
と、第ｎ＋１遅延回路の出力信号と第ｎ＋１排他
的論理和回路の出力信号との排他的論理和をとる
Ｎ−１個の第２排他的論理和回路〜第Ｎ−１排他
的論理和回路と、この第Ｎ−１排他的論理和回路
の出力信号から入力信号の周波数のＮ倍にてい倍
された信号を抽出する共振回路とからなるＮ倍周
波数てい倍回路。 For an input signal with a period T, a first delay circuit having a delay time of T/2N is connected to N-1 second delay circuits having different delay times in steps of T/2N to an N-th delay circuit.
1 delay circuit, a first exclusive OR circuit that takes an exclusive OR of the input signal and the output signal of the first delay circuit, an output signal of the n+1-th delay circuit, and an output signal of the n+1-th exclusive OR circuit. The frequency of the input signal is determined from the output signal of the N-1 second exclusive OR circuit to the N-1st exclusive OR circuit and the output signal of this N-1st exclusive OR circuit. An N-times frequency multiplier circuit consisting of a resonant circuit that extracts a signal multiplied by N times.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1150787U JPS63121916U (en) | 1987-01-30 | 1987-01-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1150787U JPS63121916U (en) | 1987-01-30 | 1987-01-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63121916U true JPS63121916U (en) | 1988-08-08 |
Family
ID=30798787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1150787U Pending JPS63121916U (en) | 1987-01-30 | 1987-01-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63121916U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005295542A (en) * | 2004-04-02 | 2005-10-20 | Tektronix Inc | Linearity compensation circuit |
-
1987
- 1987-01-30 JP JP1150787U patent/JPS63121916U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005295542A (en) * | 2004-04-02 | 2005-10-20 | Tektronix Inc | Linearity compensation circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH02141135U (en) | ||
| JPS63121916U (en) | ||
| JPS611926U (en) | Pulse duty shaping circuit | |
| JPS63163028U (en) | ||
| JPS6356826U (en) | ||
| JPH0439740U (en) | ||
| JPS60158161U (en) | frequency/voltage converter | |
| JPH0357630U (en) | ||
| JPS63140732U (en) | ||
| JPH01153736U (en) | ||
| JPS62129845U (en) | ||
| JPS62151237U (en) | ||
| JPS61136635U (en) | ||
| JPH0476725U (en) | ||
| JPS633629U (en) | ||
| JPH0163224U (en) | ||
| JPS61154025U (en) | ||
| JPH0163213U (en) | ||
| JPH0481063U (en) | ||
| JPS62134076U (en) | ||
| JPS59138770U (en) | Sampling pulse generation circuit | |
| JPS6264033U (en) | ||
| JPS6064616U (en) | frequency multiplier | |
| JPH0221925U (en) | ||
| JPH0312528U (en) |