JPH0221925U - - Google Patents
Info
- Publication number
- JPH0221925U JPH0221925U JP9945888U JP9945888U JPH0221925U JP H0221925 U JPH0221925 U JP H0221925U JP 9945888 U JP9945888 U JP 9945888U JP 9945888 U JP9945888 U JP 9945888U JP H0221925 U JPH0221925 U JP H0221925U
- Authority
- JP
- Japan
- Prior art keywords
- exclusive
- signal
- input signal
- outputting
- delayed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案に係る逓倍器の一実施例を示し
た概略構成図、第２図は第１図に示した逓倍器の
動作を示すタイミングチヤート、第３図は本考案
に係る逓倍器の他の実施例を示した概略構成図、
第４図は第３図に示した逓倍器の動作を示すタイ
ミングチヤートである。
１，１０……入力端子、２Ａ，２Ｂ，２Ｃ，２
Ｄ，２Ｅ，２０Ａ，２０Ｂ……ドライバ回路、３
Ａ，３Ｂ，３Ｃ，３Ｄ，３Ｅ，３０Ａ，３０Ｂ…
…遅延素子、４Ａ，４Ｂ，４Ｃ，４Ｄ，４Ｅ，４
０Ａ，４０Ｂ……排他的論理和回路、５，５０…
…出力端子。
Fig. 1 is a schematic configuration diagram showing an embodiment of the multiplier according to the present invention, Fig. 2 is a timing chart showing the operation of the multiplier shown in Fig. 1, and Fig. 3 is a multiplier according to the present invention. A schematic configuration diagram showing another example of
FIG. 4 is a timing chart showing the operation of the multiplier shown in FIG. 1, 10...Input terminal, 2A, 2B, 2C, 2
D, 2E, 20A, 20B...driver circuit, 3
A, 3B, 3C, 3D, 3E, 30A, 30B...
...Delay element, 4A, 4B, 4C, 4D, 4E, 4
0A, 40B...exclusive OR circuit, 5, 50...
...Output terminal.
Claims (1)
周波数の整数倍の逓倍信号を出力する逓倍器にお
いて、 前記入力信号を所定の時間、遅延して出力する
遅延手段と、 前記遅延手段の出力信号と前記入力信号との排
他的論理和をとり、この結果を出力する排他的論
理和手段と、 を具え、前記排他的論理和手段から逓倍信号を出
力するようにしたことを特徴とする逓倍器。 (2) 少なくとも２つの遅延回路を有し、所定の
周波数の入力信号をそれぞれ所定時間、遅延して
出力する遅延手段と、 少なくとも２つの排他的論理和回路を有し、前
記遅延手段の出力信号と前記入力信号との排他的
論理和をとり、この結果を出力するとともに、先
にとつた排他的論理和回路の出力信号と、該先に
とつた排他的論理和回路において入力され所定時
間、遅延された入力信号よりもさらに遅延された
前記遅延手段の出力信号との排他的論理和を順次
とり、その結果を出力する排他的論理和手段と を具え、前記入力周波数の所望の整数倍の逓倍信
号を出力することを特徴とする逓倍器。[Claims for Utility Model Registration] (1) A multiplier that receives an input signal of a predetermined frequency and outputs a signal multiplied by an integral multiple of the input frequency, the input signal being delayed for a predetermined time and output. a delay means; an exclusive OR means for taking an exclusive OR of the output signal of the delay means and the input signal and outputting the result; the exclusive OR means outputting a multiplied signal. A multiplier characterized by: (2) a delay means having at least two delay circuits, each delaying an input signal of a predetermined frequency by a predetermined time and outputting the delayed signal; and at least two exclusive OR circuits, the output signal of the delay means and the input signal and outputs this result, and the output signal of the previously taken exclusive OR circuit and the input signal of the previously taken exclusive OR circuit for a predetermined time, an exclusive OR means for sequentially performing an exclusive OR with the output signal of the delay means that is delayed further than the delayed input signal, and outputting the result; A multiplier characterized by outputting a multiplied signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9945888U JPH0221925U (en) | 1988-07-27 | 1988-07-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9945888U JPH0221925U (en) | 1988-07-27 | 1988-07-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0221925U true JPH0221925U (en) | 1990-02-14 |
Family
ID=31326636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9945888U Pending JPH0221925U (en) | 1988-07-27 | 1988-07-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0221925U (en) |
-
1988
- 1988-07-27 JP JP9945888U patent/JPH0221925U/ja active Pending
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