JP5858281B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a high frequency power amplifier for amplifying an RF (Radio Frequency) signal, and more particularly to an effective technique for correcting variation in characteristics of the high frequency power amplifier.

  In recent years, in the mobile phone market, in addition to the GSM (Global System for Mobile Communications) method that represents the second generation mobile phone (2G: 2nd Generation), the W-CDMA (Wideband-Code Division Multiple Access) method is used. The mobile phone (3G) market has begun to rise rapidly.

  A cellular phone amplifies an RF signal generated based on a baseband signal by a high frequency power amplifier and transmits the amplified RF signal. This high-frequency power amplifier is often configured as one electronic component in which a semiconductor chip including an amplifying transistor and its bias circuit, and discrete components constituting a peripheral circuit are mounted on a multilayer substrate. This electronic component is called, for example, a HPA (High Power Amplifier) module.

  The HPA module for transmission in a GSM mobile phone forms a feedback loop by an APC (Auto Power Control) circuit that adjusts the amplification factor (gain) of an amplifier circuit that amplifies an RF signal, a power detection circuit, and an error amplifier. The minor loop control system is configured to control so as to obtain an RF signal having a target power level. On the other hand, the HPA module for transmission in the third generation mobile phone fixes the gain by fixing the DC bias point of the amplifying transistor that constitutes the amplifier circuit, and changes the power of the input RF signal to change the target. The bias fixed / variable input power control method (open loop method) is controlled so as to obtain an RF signal having a power level of In particular, an HPA module for transmission in a W-CDMA mobile phone includes a semiconductor chip incorporating an amplifier circuit formed by an HBT (Heter Junction Bipolar Transistor) process excellent in small and highly accurate high-frequency characteristics, and the amplifier circuit In many cases, the semiconductor device is realized by a two-chip configuration of a semiconductor chip having a built-in bias circuit for supplying a bias voltage and configured by a CMOS process.

  In the HPA module of the bias-fixed / variable input power control system, characteristics such as gain, efficiency, and linearity of the amplifier circuit change when the idle current flowing through the amplification transistor constituting the amplifier circuit changes. For example, if the characteristics of the amplifying transistors vary between HPA modules due to manufacturing variations, the idle current of each amplifying transistor will have a different value even if the same bias voltage is supplied. And characteristics such as linearity vary. Therefore, it is necessary to suppress variations in idle current flowing through the amplifying transistor in the bias-fixed / variable input power control type HPA module.

  Patent Documents 1 and 2 disclose conventional techniques for adjusting a bias current of an amplifying transistor in a high-frequency power amplifier. The high frequency power amplifier circuit disclosed in Patent Document 1 generates a voltage based on a current flowing through a power simulating transistor formed with the same channel length and the same process as the amplifying transistor, and the voltage becomes a reference voltage. Feedback control is performed so that they are equal. As a result, the bias point shift due to the short channel effect of the amplifying transistor is corrected, and variations in amplification characteristics between chips are reduced.

  The amplifier disclosed in Patent Document 2 initializes the bias voltage of the amplifying transistor by referring to a bias setting table storing operating conditions of the amplifier based on the detected temperature. After that, the amplifier refers to the table based on the detected power supply voltage value, reads the target set current value, and detects the bias current of the amplification transistor. Then, the adjustment of the bias voltage and the detection of the bias current are repeated until the detected bias current falls within a predetermined error range with respect to the set current. Since various controls using the table are performed by digital control, the amplifier includes a plurality of digital / analog conversion circuits (DAC) and analog / digital conversion circuits (ADC).

JP 2005-123861 A JP 2005-197904 A

  However, as in Patent Document 1, if the bias point of the amplifying transistor is stabilized by minor loop control by a feedback circuit, the RF signal may be adversely affected. For example, if the frequency band of the feedback circuit and a part of the frequency band of the RF signal overlap, the RF signal in the overlapping frequency band may be modulated by the feedback circuit, and the linearity of the RF signal may be deteriorated.

  On the other hand, in a configuration using a DAC or ADC as in Patent Document 2, a clock signal is required depending on the circuit configuration, and the clock signal may become noise and adversely affect the RF signal to be transmitted. Further, the method of Patent Document 2 requires processing such as detection of a power supply voltage and temperature in addition to detection of a bias current, and it takes time to determine the bias current. Furthermore, since the method of Patent Document 2 requires the table and a plurality of DACs and ADCs, the circuit scale increases and the cost increases. In particular, since the HPA module for transmission in a W-CDMA mobile phone is often realized with a two-chip configuration as described above, further increase in cost is not preferable.

  As another method, in an HPA module implemented with a two-chip configuration, an HPA module conforming to a desired standard can be obtained without providing a circuit for compensating for the above-described variation in characteristics of the high-frequency power amplifier. In addition, the following method can be employed. For example, the characteristics of the semiconductor chip that constitutes the amplifier circuit and the semiconductor chip that constitutes the bias circuit are measured and sorted for each characteristic variation, and the characteristics of the HPA module as a whole (characteristics such as gain, efficiency, and linearity) ) Is a method for determining a combination of two semiconductor chips so as to conform to a target standard. However, this method requires an operation for classifying the chips for each characteristic and an operation for combining the classified chips according to the characteristics at the time of manufacturing, resulting in an increase in manufacturing cost.

  An object of the present invention is to realize stable characteristics independent of manufacturing variations in a semiconductor device including a high-frequency power amplifier.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  An outline of typical inventions disclosed in the present application will be briefly described as follows.

  That is, the semiconductor device includes a high-frequency amplifier including one or more transistors that amplify and output an input RF signal, and a bias voltage generator that generates a bias voltage of the high-frequency amplifier. The bias voltage generation unit performs a determination process to determine which current range of a plurality of preset current ranges includes a monitor current proportional to an idle current flowing through the transistor. A voltage corresponding to the current range is generated and output as the bias voltage.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to this, it is possible to realize a high-frequency power amplifier having stable characteristics independent of manufacturing variations.

FIG. 1 is a block diagram showing a circuit configuration of the RF signal transmitting HPA module according to the first embodiment. FIG. 2 is a block diagram for explaining the generation principle of the idle current Icq4 of the transistor Q4. FIG. 3 is an explanatory diagram illustrating the variation characteristic of the collector current Icq1. FIG. 4 is an explanatory diagram showing the gain characteristics of the high-frequency amplifier 11. FIG. 5 is an explanatory diagram illustrating the efficiency characteristics of the high-frequency amplifier 11. FIG. 6 is an explanatory diagram showing the linearity characteristics of the high-frequency amplifier 11. FIG. 7 is an explanatory diagram illustrating an example of variation correction of the idle current Icq4. FIG. 8 is a flowchart showing an example of the operation flow of each circuit block in the HPA module 1 after the power is turned on. FIG. 9 is a block diagram showing a circuit configuration of the RF signal transmitting HPA module according to the second embodiment. FIG. 10 is a block diagram showing a circuit configuration of the RF signal transmitting HPA module according to the third embodiment. FIG. 11 is a block diagram showing a circuit configuration of an RF signal transmitting HPA module according to the fourth embodiment.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] (Semiconductor device that adjusts the bias voltage according to the degree of variation in idle current of the high-frequency amplifier circuit)
A semiconductor device (1 to 4) according to a typical embodiment of the present invention includes a high frequency amplifier (11, 21, 31, 41) for performing power amplification of an input RF signal, and the high frequency amplifier. And a bias voltage generation unit (10, 40) for generating a bias voltage (Vcont). The high frequency amplifier unit determines a bias state of the transistor based on one or a plurality of transistors (Q4, Q8) that amplify and output the input RF signal and a bias voltage generated by the bias voltage generator. A bias control unit (111, 211); and a current generation unit (110, 210) that generates a monitor current (Icont, Icont1, Icont2) proportional to an idle current (Icq4, Icq8) flowing through the transistor. The bias voltage generation unit performs a determination process for determining which current range (801 to 803) is included in a plurality of preset current ranges, and includes the determined current range. A corresponding voltage is generated and output as the bias voltage.

  According to this, even if the idle current of the transistor varies, it is possible to suppress variation in characteristics of the high-frequency amplifier circuit between the semiconductor devices. In addition, since no feedback loop is formed to stabilize the DC bias point, the linearity of the high-frequency amplifier circuit is not adversely affected. Furthermore, since the bias voltage is determined according to the determined current range, the bias state can be quickly corrected and stabilized.

[2] (Distinction result is retained and initialized by reset signal)
In the semiconductor device according to Item 1, the bias voltage generation unit includes a determination unit (102, 103, CMP1, CMP2, 105, 106 (102_1, 102_2, 103_1, 103_2, CMP3, CMP4, 107) for performing the determination process. 108)), a volatile storage unit (FF1, FF2 (FF3, FF4)) that holds the determination result by the determination unit, and a regulator that generates the bias voltage according to the determination result held in the storage unit Circuit (101, (101_1, 101_2)). The storage unit is configured to be able to initialize stored information by a reset signal (RST).

  According to this, if the determination process is performed only once after the reset signal is released, the determination result is held in the storage unit, so that an unexpected monitor current due to a change in operating environment, noise, or the like is unexpected. There is no possibility that the bias voltage is switched due to a change, and stable operation of the high-frequency amplifier can be expected.

[3] (Power-on reset)
In the semiconductor device according to Item 2, the reset signal is a power-on reset signal.

  According to this, since the determination process is performed only once after the power-on reset is released after the power is turned on and the bias voltage is determined, it is not necessary for the user to separately prepare a circuit for generating the reset signal.

[4] (Specific configuration of bias voltage generator)
In the semiconductor device according to Item 2 or 3, the determination unit includes a current-voltage conversion unit (103 (103_1, 103_2)) that converts the monitor current into a voltage, and a reference that generates a plurality of different reference voltages (Vr5, Vr45). Voltage generator (102 (102_1, 102_2)). The discriminator is provided corresponding to each reference voltage, and compares the corresponding reference voltage with the converted voltage and outputs a comparison result (CMP1, CMP2 (CMP3, CMP4)). ). The storage unit holds the comparison result output from each of the comparators as the determination result.

  According to this, it is possible to easily realize the function of determining which current range the idle current is in. Accordingly, various tables and a plurality of DACs and ADCs are not required as in Patent Document 2, and an increase in circuit scale can be suppressed. Furthermore, according to the circuit configuration of the semiconductor device of Item 4, the number of current ranges (current detection accuracy) set according to the number of reference voltages and the number of comparators corresponding thereto can be adjusted. It becomes easy to change the circuit according to the standard to be used.

[5] (Two semiconductor devices)
In the semiconductor device according to any one of Items 1 to 4, the high-frequency amplification unit and the bias voltage generation unit are configured on separate semiconductor substrates.

  According to this, the respective characteristics of the two semiconductor devices are measured as in the prior art and sorted for each characteristic variation, so that the power amplification characteristics of the entire HPA module are within the target standard range. Since the operation of combining the semiconductor devices is not necessary, an increase in manufacturing cost can be suppressed.

[6] (Individual bias adjustment)
In the semiconductor device (4) according to any one of Items 1 to 5, a plurality of the transistors (Q4, Q8) are cascade-connected, and the high-frequency amplifier (41) includes the bias controller (111, 111) for each transistor. 211) and the current generator (110, 210). The bias voltage generation unit performs the determination process on the monitor currents (Icont1, Icont2) generated by the current generation units, and generates the bias voltages (Vcont1, Vcont2) generated according to the determination results. ) To the corresponding bias control section.

  According to this, even when the amplifier circuit is composed of multiple amplifier stages, the characteristics of the individual amplifier stages can be adjusted with higher accuracy.

[7] (Common bias voltage is adjusted based on one idle current)
In the semiconductor device (2, 3) according to any one of Items 1 to 5, a plurality of the transistors (Q4, Q8) are cascade-connected, and the high-frequency amplification unit is configured to have the bias control unit (111, 211) for each transistor. ). The current generation unit (110 (210)) generates the monitor current related to any one of the plurality of transistors (Q4 (Q8)). Further, the bias voltage generation unit (10) outputs the generated voltage to each of the bias control units as a common bias voltage (Vcont).

  According to this, even when the amplifier circuit is composed of a plurality of amplifier stages, it is possible to accurately suppress variations in characteristics of the entire amplifier circuit while suppressing the circuit scale.

[8] (Monitor the idle current of a transistor with high sensitivity to bias voltage)
In the semiconductor device (2) according to Item 7, the one transistor is a transistor (Q4) having the largest change rate of the idle current with respect to the change of the bias voltage among the plurality of transistors.

  For example, when the sensitivity of the idle current with respect to the bias voltage of each amplifying transistor is greatly different, the bias voltage is determined so that the idle current of the most sensitive transistor becomes an optimum value as in Item 8, Variations in characteristics of the entire amplifier circuit can be suppressed with higher accuracy.

[9] (Monitor the transistor with the higher idle current)
In the semiconductor device (3) according to Item 7, the one transistor is a transistor (Q8) having the largest idle current among the plurality of transistors.

  For example, when the idle current of one of a plurality of amplifying transistors is sufficiently larger than the other transistors, the largest variation in idle current greatly affects the characteristics of the entire amplifier circuit. Therefore, according to the semiconductor device of item 9, variation in characteristics of the entire amplifier circuit can be suppressed more accurately.

2. Details of Embodiments Embodiments will be further described in detail.

<< Embodiment 1 >>
FIG. 1 is a block diagram showing a circuit configuration of the HPA module according to the present embodiment.

  The HPA module 1 shown in the figure is used as a power amplifier for transmission in, for example, a W-CDMA mobile phone. The HPA module 1 includes, for example, a high frequency amplification unit (AMP) 11 for performing power amplification of an RF signal, a bias voltage generation unit (BIAS) 10 for supplying a bias voltage to the high frequency amplification unit 11, and other peripherals A circuit is a semiconductor device configured as one electronic component mounted on a multilayer substrate.

  The high frequency amplifier 11 and the bias voltage generator 10 are separate semiconductor chips formed on separate semiconductor substrates, for example. The respective semiconductor chips are connected to each other by, for example, bonding wires. For example, the terminal VCONT_OUT of the bias voltage generation unit 10 and the terminal VCONT_IN of the high frequency amplification unit 11 are connected to each other by a bonding wire, and the terminal ICONT_IN of the bias voltage generation unit 10 and the terminal ICONT_OUT of the high frequency amplification unit 11 are connected to each other by a bonding wire. Connected with.

  The high-frequency amplifier 11 is not particularly limited, but is formed on a single compound semiconductor substrate such as GaAs by a known hetero-coupled bipolar transistor (HBT) manufacturing technique. The high frequency amplifier 11 includes, for example, a bipolar transistor (hereinafter also simply referred to as a transistor) Q4 formed by an HBT process that constitutes an amplifier circuit, and a bias controller 111 that supplies a bias current (base current) to the transistor Q4. The current generator 110 generates a monitor current proportional to the idle current of the transistor Q4, and other peripheral circuits. The transistor Q4 is connected to the ground node on the emitter side, and connected to the inductor L via the terminal POUT on the collector side, thereby constituting a grounded emitter amplifier circuit. For example, when an RF signal to be transmitted output from a signal source such as the RFIC 5 provided outside is input to the terminal PIN, it is input to the base of the transistor Q4 via the matching circuit (MCG_CIR) 112, and the transistor Q4 Amplifies the RF signal and outputs it from the terminal POUT. The bias state of the transistor Q4 is controlled by the bias controller 111. Specifically, the current generated based on the bias voltage Vcont supplied from the bias voltage generator 10 by the bias controller 111 is supplied as the base current of the transistor Q4. The bias control unit 111 includes, for example, resistors Rb1 and Rbb1 and transistors Q1A, Q2, and Q3, and their connection relations are as follows. The resistor Rb1 has one end connected to the terminal VCONT_IN to which the bias voltage Vcont is supplied and the other end connected to one end of the resistor Rbb1 and the collector of the transistor Q2. Transistor Q2 has a diode connection in which the collector and base are short-circuited, and the emitter is connected to the collector of transistor Q1A. Similarly, transistor Q1A is also diode-connected, and its emitter is connected to the ground node. The resistor Rbb1 has one end connected to the resistor Rb1 and the collector of the transistor Q2, and the other end connected to the base of the transistor Q3. Transistor Q3 has a collector connected to terminal VIN for inputting voltage Vbatt from the external battery, and an emitter connected to the base of transistor Q4 via a resistor. According to the above circuit configuration, a current corresponding to the bias voltage Vcont is output from the emitter of the transistor Q3 and supplied to the base of the transistor Q4. Thereby, the bias state of the transistor Q4 is determined, and a collector current (idle current) Icq4 corresponding thereto flows. The characteristics of the amplifier circuit such as gain, efficiency, and linearity are determined by the magnitude of the idle current Icq4 of the transistor Q4. On the other hand, a collector current Icq1 proportional to the idle current of the transistor Q4 in the amplification stage flows through the collector of the diode-connected transistor Q1A. For example, when the emitter area ratio of the transistor Q4 and the transistor Q1A is n (n is an integer equal to or greater than 1) to 1, the collector current Icq1 of the transistor Q1A is about 1 / n of the idle current Icq4 of the transistor Q4. Note that the error component increases as the emitter area ratio increases, so that the amount of deviation of the current ratio (1 / n) increases. Details of the collector current Icq1 will be described later.

  Current generator 110 outputs monitor current Icont obtained by monitoring the idle current of transistor Q4. Specifically, the current generator 110 is a current mirror circuit using the transistor Q1A and the transistor Q1B, and outputs a current obtained by mirroring the collector current Icq1 from the terminal ICOUT_OUT as the monitor current Icont. Although not particularly limited, in this embodiment, the current mirror ratio is set to 1: 1.

  As described above, the bias voltage generation unit 10 generates the bias voltage Vcont to be supplied to the high frequency amplification unit 11. The bias voltage generator 10 is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit manufacturing technique.

  The bias voltage generation unit 10 includes a band gap constant voltage circuit 100 and a regulator unit 101. The band gap constant voltage circuit 100 is a voltage source that generates a voltage Vbgr using the band gap of silicon. The voltage Vbgr is about 1.23 V, for example, and is used as a reference voltage for each block.

  The regulator unit 101 generates and outputs a bias voltage Vcont. The regulator unit 101 includes, for example, an amplifier OP1, resistors R2A, R2B, R1A, and R1B, switches SW1 and SW2, and a capacitor C1, and the connection relationship between them is as follows. The voltage Vbgr is supplied to the non-inverting input terminal of the amplifier OP1, and the voltage from the resistance ladder is supplied to the inverting input terminal. The output terminal of the amplifier OP1 is connected to the terminal VCONT_OUT. The resistor ladder and the stabilization capacitor C1 are connected between the output terminal of the amplifier and the ground node. The resistor ladder includes a resistor R2A, a resistor R2B, a resistor R1A, and a resistor R1B connected in series. Specifically, one end of the resistor R2A is connected to the output terminal of the amplifier OP1, and the other end is connected to one end of the resistor R2B. The other end of the resistor R2B is connected to one end of the resistor R1A and to the inverting input terminal of the amplifier OP1. A switch SW2 is connected to both ends of the resistor R2B. The resistor R1B has one end connected to the other end of the resistor R1A and the other end connected to the ground node. A switch SW1 is connected to both ends of the resistor R1B. According to the circuit configuration described above, the amplifier OP1 generates an output voltage so that the voltage Vn at the inverting input terminal is equal to the voltage Vbgr at the non-inverting input terminal. This output voltage is output from the terminal VCONT_OUT as the bias voltage Vcont. The magnitude of the bias voltage Vcont is determined based on the resistance ratio between the resistance component R2 between the node of the voltage Vcont and the node of the voltage Vn and the resistance component R1 between the node of the voltage Vn and the ground node. . The resistance value of the resistance component R1 can be adjusted by turning on / off the switch SW1, and the resistance value of the resistance component R2 can be adjusted by turning on / off the switch SW2. A specific adjustment method will be described later.

  Here, the relationship between the bias voltage Vcont and the idle current Icq4 of the transistor Q4 in the high frequency amplifier 11 will be described in detail.

  FIG. 2 is a block diagram for explaining the generation principle of the idle current Icq4 of the transistor Q4. In the drawing, only the circuit blocks necessary for the present description among the circuit blocks constituting the HPA module 1 are illustrated and simplified.

  As described above, the idle current Icq4 of the transistor Q4 and the collector current Icq1 of the transistor Q1A are in a proportional relationship. For example, when the collector current Icq1 of the transistor Q1A increases, the idle current Icq4 of the transistor Q4 also increases proportionally. From the circuit configuration shown in FIG. 2, the collector current Icq1 of the transistor Q1A is expressed by (Expression 1), and the bias voltage Vcont is expressed by (Expression 2). In order to facilitate understanding, in the following calculation formulas including (Formula 1) and (Formula 2), the base current of the bipolar transistor is ignored.

  As shown in (Formula 1), the collector current Icq1 of the transistor Q1A depends on the magnitude of the bias voltage Vcont. Therefore, by adjusting the bias voltage Vcont, it is possible to adjust the idle current Icq4 of the transistor Q4 and adjust characteristics such as gain, efficiency, and linearity as an amplifier circuit of the high frequency amplifier 11.

  Here, the variation of the collector current Icq1 is considered. The collector current Icq1 varies in characteristics due to variations in the bias voltage Vcont, the base-emitter voltage Vbe of the bipolar transistors Q1A and Q2, and the resistance Rb1, as represented by (Equation 1). When this is expressed by an equation, for example, (Equation 3) is obtained.

  Similarly, the characteristic considering the variation of the bias voltage Vcont is expressed as (Equation 4). It is assumed that the resistors R1 and R2 are formed of the same type of resistors and are so small that relative variations can be ignored.

  Here, for example, assuming that Vcont = 2.8V, ΔVcont = 0.1V, 2Vbe = 2.55V, ΔVbe = 0.02V, and ΔRb1 = 15%, the variation in the collector current Icq1 is expressed by (Formula 5).

  When this is graphed, the characteristics of the collector current Icq1 are as shown in FIG. 3, for example.

  FIG. 3 is an explanatory diagram illustrating the variation characteristic of the collector current Icq1. In the figure, the vertical axis represents the magnitude [mA] of the collector current Icq1, and the horizontal axis represents the deviation ΔRb1 [%] of the resistance Rb1 from the target value. The characteristic indicated by reference character I_1 is the collector current Icq1 when ΔVcont = −0.1V, the characteristic indicated by reference character I_2 is the collector current Icq1 when ΔVcont = 0V, and the characteristic indicated by reference character I_3. Represents the collector current Icq1 when ΔVcont = + 0.1V, respectively.

  As shown in the figure, it is understood that the collector current Icq1 varies from about 0.5 times to about 3 times the target value. As described above, since the characteristics such as the gain, efficiency, and linearity of the high frequency amplifier 11 depend on the magnitude of the collector current Icq1, the variation in the collector current Icq1 varies with the gain, efficiency, and linearity of the high frequency amplifier 11. This leads to variations in characteristics such as characteristics.

  Here, FIGS. 4 to 6 illustrate changes in the gain, efficiency, and linearity characteristics of the high-frequency amplifier 11 when the values of the resistor Rb1 and the bias voltage Vcont are changed. 4 shows the gain characteristic of the high-frequency amplifier 11, FIG. 5 shows the efficiency characteristic of the high-frequency amplifier 11, and FIG. 6 shows the linearity characteristic of the high-frequency amplifier 11.

  In FIG. 4, the vertical axis represents the magnitude [dB] of the amplification factor (Gain), and the horizontal axis represents the deviation ΔRb1 [%] of the resistance Rb1 from the target value. The characteristic indicated by reference sign G_1 is the gain when ΔVcont = −0.1V, the characteristic indicated by reference sign G_2 is the gain when ΔVcont = 0V, and the characteristic indicated by reference sign G_3 is ΔVcont = + 0. Each represents the gain at 1V.

  In FIG. 5, the vertical axis represents the efficiency [Efficiency] magnitude [%], and the horizontal axis represents the deviation ΔRb1 [%] of the resistance Rb1 from the target value. The characteristic indicated by reference symbol E_1 is the efficiency when ΔVcont = −0.1V, the characteristic indicated by reference symbol E_2 is the efficiency when ΔVcont = 0V, and the characteristic indicated by reference symbol E_3 is ΔVcont = + 0. Each represents the efficiency at 1V.

  In FIG. 6, the vertical axis represents the magnitude [dBc] of the adjacent channel leakage power ratio (ACLR1), which is one of the indexes representing linearity, and the horizontal axis represents the deviation ΔRb1 [%] of the resistance Rb1 from the target value. Represents. The characteristic indicated by reference symbol A_1 is ACLR1 when ΔVcont = −0.1V, the characteristic indicated by reference symbol A_2 is ACLR1 of ΔVcont = 0V, and the characteristic indicated by reference symbol A_3 is ΔVcont = + 0.1V. Each ACLR1 is represented.

  4 to 6, it is understood that the collector current Icq1 and the idle current Icq4 vary due to variations in the resistance Rb1 and the bias voltage Vcont, and the gain, efficiency, and ACLR1 characteristics vary. Therefore, in the HPA module 1 according to the first embodiment, the bias voltage generation unit 10 adjusts the bias voltage Vcont according to the magnitude of the monitor current Icont that monitors the idle current Icq4, thereby correcting variations in the idle current Icq4. To do.

  FIG. 7 is an explanatory diagram showing an example of variation correction of the idle current Icq4 in the HPA module 1.

  In the figure, as an example, the variation range when the target value of the idle current Icq4 is 50 mA is illustrated. In the HPA module 1, the variation range of the idle current Icq4 is divided into three current ranges indicated by reference numerals 801 to 803, and the bias voltage generation unit 10 determines to which current range the idle current Icq4 belongs. The bias voltage generation unit 10 determines the magnitude of the bias voltage Vcont according to the determination result. For example, when the magnitude of the idle current Icq4 is within the range of the reference numeral 801, the bias voltage Vcont is increased and the magnitude of the idle current Icq4 is within the range of the reference numeral 802. In addition, when the magnitude of the idle current Icq4 is within the range of the reference numeral 803, the bias voltage Vcont is lowered and the magnitude of the idle current Icq4 is within the range of the reference numeral 802. When the magnitude of the idle current Icq4 is in the range of reference numeral 802, no correction is performed. With the above correction, the variation in the idle current Icq4 can be kept within the range of the reference numeral 802.

  The bias voltage generation unit 10 is a specific function unit for correcting variations in the idle current Icq4, in addition to the band gap constant voltage circuit 100 and the regulator circuit 101, a reference voltage generation circuit 102, a current-voltage conversion circuit 103, a comparison Devices CMP1 and CMP2, delay circuits 105 and 106, flip-flop circuits FF1 and FF2, and a reset circuit (PWR_ON_RST) 104. The reference voltage generation circuit 102, the current-voltage conversion circuit 103, and the comparators CMP1 and CMP2 are functional units for determining which current range is included in a plurality of preset current ranges. Configure. Hereafter, each circuit block which comprises the said function part is demonstrated in detail.

  The current-voltage conversion circuit 103 converts the monitor current Icont into a voltage. Specifically, the monitor current Icont flowing from the transistor M1 through the terminal ICON_IN to the terminal ICONT_OUT of the high frequency amplifier 11 is turned back by a current mirror circuit including the transistors M1 and M2 and input to one end of the resistor Rs. The other end of the resistor Rs is connected to the ground node, and the voltage Vs across the resistor Rs is “Rs · Icont”. The reference voltage generation unit 102 generates reference voltages Vr45 and Vr5 based on the voltage Vbgr. Here, Vr5 = Vbgr × R5 / (R3 + R4 + R5) and Vr45 = Vbgr × (R4 + R5) / (R3 + R4 + R5).

  The comparator CMP1 compares the reference voltage Vr5 with the voltage Vs. In the comparator CMP1, the voltage Vr5 is input to the non-inverting input terminal, and the voltage Vs is input to the inverting input terminal. The comparator CMP2 compares the reference voltage Vr45 with the voltage Vs. In the comparator CMP2, the voltage Vs is input to the non-inverting input terminal, and the reference voltage Vr45 is input to the inverting input terminal. The comparison results (X2, X1) of the comparator CMP2 and the comparator CMP1 are as follows. For example, when Vs <Vr5 (Icont <Vr5 / Rs), the comparison result (X2, X1) = (L (Low), H (High)), and Vr5 <Vs <Vr45 (Vr5 / Rs <Icont <Vr45 / When Rs), the comparison result (X2, X1) = (L, L), and when Vr45 <Vs (Vr45 / Rs <Icont), the comparison result (X2, X1) = (H, L). This makes it possible to determine which of the three current ranges (Icont <Vr5 / Rs, Vr5 / Rs <Icont <Vr45 / Rs, Vr45 / Rs <Icont) is included in the monitor current Icont. The discrimination result is represented by 2 bits of comparison results X1 and X2. The current range “Icont <Vr5 / Rs” corresponds to, for example, the range indicated by reference numeral 801 in FIG. 7, and the current range “Vr5 / Rs <Icont <Vr45 / Rs” corresponds to the range indicated by reference numeral 802. The range “Vr45 / Rs <Icont” corresponds to the range of reference numeral 803.

  The determination result is held in the flip-flop circuits FF1 and FF2. For example, the comparison result X2 of the comparator CMP2 is held in the flip-flop circuit FF2, and the comparison result X1 of the comparator CMP1 is held in the flip-flop circuit FF1. As a result, even if the comparison result changes due to an unexpected change in the monitor current due to a change in the operating environment, noise, or the like, the initially performed discrimination result can be stably held. Information held by the reset signal RST is initialized in the flip-flop circuits FF1 and FF2. The reset signal RST is not particularly limited, but is a power-on reset signal. For example, a power-on reset signal output from a reset circuit (PWR_ON_RST) 104 that monitors a power supply voltage (for example, a voltage Vbatt input to the terminal VBATT). Thus, the determination result of the monitor current Icont is not held in the flip-flop circuits FF1 and FF2 until the power-on reset state is released, and the information once held is not initialized until the power is turned off. That is, the monitor current Icont is determined only once after the power-on reset is canceled.

  A delay circuit 105 is inserted between the comparator CMP1 and the flip-flop circuit FF1, and a delay circuit 106 is inserted between the comparator CMP2 and the flip-flop circuit FF2. The delay circuits 105 and 106 delay the input comparison result for a predetermined time and output it. The delay circuits 105 and 106 are, for example, timer circuits. Thereby, it is possible to prevent an erroneous determination result from being held due to an instantaneous change in the monitor current caused by noise or the like.

  Information held in the flip-flop circuits FF1 and FF2 is used as a control signal for controlling the switches SW1 and SW2 in the regulator unit 101. The switches SW1 and SW2 are composed of, for example, MOS transistors. For example, the switch SW1 is turned on when the output signal SQ1 of the flip-flop circuit FF1 is “H (High)”, and the switch SW1 is turned off when the output signal SQ1 is “L (Low)”. When the output signal SQ2 of the flip-flop circuit FF2 is “H”, the switch SW2 is turned on, and when the output signal SQ2 is “L”, the switch SW2 is turned off. Accordingly, the resistance value of the resistance component R1 can be switched between “R1A” and “R1A + R1B”, and the resistance value of the resistance component R2 can be switched between “R2A” and “R2A + R2B”. By making it possible to change the resistance values of the resistance components R1 and R2, the bias voltage Vcont can be increased or decreased. Note that the switches SW1 and SW2 may be directly driven by the output signals SQ1 and SQ2 of the flip-flop circuits FF1 and FF2, or a driver circuit for driving the switches SW1 and SW2 at the subsequent stage of the flip-flop circuits FF1 and FF2. A separate driver circuit may drive the switches SW1 and SW2.

  A method for determining the bias voltage Vcont in the HPA module 1 will be described in detail with reference to FIG.

  FIG. 8 is a flowchart showing an example of the operation flow of each circuit block in the HPA module 1 after the power is turned on. First, when the voltage Vbatt and the voltage Vcc are input as the power supply voltage of the HPA module 1, the power-on reset is released, the bias voltage generation unit 10 is activated, and the bias voltage Vcont is input to the terminal VCONT_IN of the high frequency amplification unit 11 (S101). At this time, the initial values of the output signals SQ1, SQ2 of the flip-flop circuits FF1, FF2 are L (Low), and the switches SW1, SW2 are in the off state. That is, the resistance value of the resistance component R1 is “R1A + R1B”, and the resistance value of the resistance component R2 is “R2A + R2B”. Therefore, the bias voltage Vcont = Vbgr × (R1A + R1B + R2A + R2B) / (R1A + R1B).

  When the bias voltage Vcont is supplied to the terminal VCONT_IN, the collector current Icq1 flows through the transistor Q1A of the bias controller 111 (S102). The collector current Icq1 is input to the bias voltage generation unit 10 as the monitor current Icont by the current generation unit 110 constituting the current mirror circuit, and is converted to the monitor voltage Vs by the resistor Rs (S103). Then, the comparators CMP1 and CMP2 compare the monitor voltage Vs with the reference voltages Vr5 and Vr45 (S104).

  In step 104, when the idle current Icq4 of the transistor Q4 is smaller than the target value, for example, Vs <Vr5 and Vs <Vr45 (current range of reference numeral 801 in FIG. 7), the output of the comparator CMP1 becomes “H”. The output of the comparator CMP2 becomes “L” (S105). As a result, the output SQ1 of the flip-flop circuit FF1 is switched to “H”, and the output SQ2 of the flip-flop circuit FF2 is held at “L” (S106). As a result, the switch SW1 of the regulator unit 10 is turned on, and the switch SW2 is kept off (S107). That is, the resistance value of the resistance component R1 is “R1A”, and the resistance value of the resistance component R2 is “R2A + R2B”. As a result, the bias voltage Vcont becomes “Vbgr × (R1A + R2A + R2B) / R1A”, and the bias voltage Vcont increases (S108). When the bias voltage Vcont increases, the collector current Icq1 increases, and the idle current Icq4 of the transistor Q4 is corrected to increase (S109).

  In step 104, when the idle current Icq4 of the transistor Q4 is within a predetermined error range from the target value, for example, Vr5 <Vs <Vr45 (current range of reference numeral 802 in FIG. 7), the output of the comparator CMP1 is “ The output of the comparator CMP2 becomes “L” (S110). As a result, the output SQ1 of the flip-flop circuit FF1 and the output SQ2 of the flip-flop circuit FF2 are both held at “L” (S111). Thereby, the switch SW1 and the switch SW2 of the regulator unit 10 are maintained in the off state (S112). That is, the bias voltage Vcont remains “Vbgr × (R1A + R1B + R2A + R2B) / (R1A + R1B)”. As a result, the idle current Icq4 of the transistor Q4 is not corrected (S113).

  In step 104, when the idle current Icq4 of the transistor Q4 is larger than the target value, for example, Vr5 <Vs and Vr45 <Vs (current range indicated by reference numeral 803 in FIG. 7), the output of the comparator CMP1 becomes “L”. The output of the comparator CMP2 becomes “H” (S114). As a result, the output SQ1 of the flip-flop circuit FF1 is held at “L”, and the output SQ2 of the flip-flop circuit FF2 is held at “H” (S115). Thereby, the switch SW1 of the regulator unit 10 is held in the off state, and the switch SW2 is changed to the on state (S116). That is, the resistance value of the resistance component R1 is “R1A + R1B”, and the resistance value of the resistance component R2 is “R2A”. As a result, the bias voltage Vcont becomes “Vbgr × (R1A + R1B + R2A) / (R1A + R1B)”, and the bias voltage Vcont decreases (S117). When the bias voltage Vcont decreases, the collector current Icq1 decreases, and the idle current Icq4 of the transistor Q4 is corrected to decrease (S118).

  As described above, according to the HPA module 1 according to the first embodiment, even if the idle current of the transistor Q4 varies due to manufacturing variations, it can be easily corrected. Therefore, characteristics such as gain, efficiency, and linearity of the high-frequency amplification unit 11 can be corrected. The variation of can be suppressed. Further, according to the HPA module 1, as described above, the characteristics of the two semiconductor chips of the high-frequency amplifier 11 and the bias voltage generator 10 are measured and sorted for each characteristic variation, and the characteristics of the entire HPA module are determined. Compared with the method of combining two semiconductor chips so that the value falls within the target standard range, the sorting operation or the like is not necessary, so that the manufacturing cost can be reduced. Further, it is not necessary to perform trimming in the manufacturing process of the HPA module, and the manufacturing cost can be reduced as compared with a method of performing trimming with a fuse (FUSE) or a bonding option. Further, the HPA module 1 determines the monitor current Icont after power-on (after power-on reset), and determines the bias voltage Vcont according to the determined current range, so that the bias of the transistor Q4 in the amplification stage is promptly determined. The state can be stabilized. Further, since a feedback loop is not formed to stabilize the bias point as in Patent Document 1 and a clock signal is not required, the linearity of the RF signal to be transmitted is not adversely affected. Since various tables as in Patent Document 2 and a plurality of DACs and ADCs are unnecessary, an increase in circuit scale can be suppressed.

  Moreover, according to the HPA module 1, it is easy to change the circuit according to the standard required by the user. For example, when it is desired to reduce the allowable error of the idle current Icq4 of the transistor Q4, the number of reference voltages by the reference voltage generation circuit 102 is increased to narrow the voltage interval, and the comparator according to the increased number of reference voltages. In addition, a flip-flop circuit may be added to reduce the adjustment width of the resistance components R1 and R2 of the regulator unit 101.

<< Embodiment 2 >>
FIG. 9 is a block diagram showing a circuit configuration of the RF signal transmitting HPA module according to the second embodiment.

  In the first embodiment, the high-frequency amplification unit 11 in the HPA module 1 is configured by a one-stage amplification circuit, but the high-frequency amplification unit 21 of the HPA module 2 shown in the figure is configured by a two-stage amplification circuit.

  In addition, the same code | symbol is attached | subjected to the component similar to the HPA module 1 among the components which comprise the HPA module 2 in FIG. 9, and the detailed description is abbreviate | omitted.

  In addition to the transistor Q4, the bias control unit 111, and the current generation unit 110 that form the first stage amplifier circuit, the high-frequency amplifier unit 21 includes a transistor Q8 that forms an output stage amplifier circuit, and a bias current (base current) to the transistor Q8. And a bias control unit 211 for supplying. Transistor Q8 is an HBT similar to transistor Q4.

  The transistor Q4 has a collector side connected to the inductor L1 via the terminal PC1 to constitute a grounded emitter amplifier circuit. For example, when an RF signal to be transmitted output from a signal source such as the RFIC 5 provided outside is input to the terminal PIN, it is input to the base of the transistor Q4 via the matching circuit (MCG_CIR) 112, and the transistor Q4 Amplifies and outputs the RF signal. The RF signal amplified by the first stage amplifier circuit is input to the base of the transistor Q8 via the matching circuit (MCG_CIR) 113 for impedance matching between the first stage amplifier circuit and the subsequent stage amplifier circuit and the capacitor. .

  The transistor Q8 has a collector side connected to the inductor L2 via the terminal POUT, and constitutes a grounded emitter amplifier circuit. The RF signal input to the base of the transistor Q8 is amplified by the transistor Q8 and output from the terminal POUT. The bias state of the transistor Q8 is controlled by the bias controller 211. Specifically, the bias controller 211 generates the base current of the transistor Q8 based on the bias voltage Vcont supplied from the bias voltage generator 10. The bias control unit 211 includes, for example, resistors Rb2 and Rbb2 and transistors Q5, Q6, and Q7, and the connection relationship between them is the same as that of the bias control unit 111. The resistors Rb2, Rbb2 and the resistors Rb1, Rbb1 are formed of the same type of resistor, and the transistors Q5, Q6, Q7 and the transistors Q1A, Q2, Q3 are all HBTs. With the above circuit configuration, the bias state of the transistor Q8 is determined, and a collector current (idle current) Icq8 corresponding thereto flows. The idle current Icq8 of the transistor Q8 determines characteristics such as gain, efficiency, and linearity of the amplifier circuit in the subsequent stage.

  Similarly to the bias control unit 111, a current Icq5 proportional to the idle current Icq8 of the transistor Q8 in the amplification stage flows through the collector of the diode-connected transistor Q5, and the current value is expressed by (Expression 6). .

  The bias voltage generation unit 10 determines the magnitude of the monitor current Icont related to the first-stage amplification transistor Q4 in the high-frequency amplification unit 21, and generates the bias voltage Vcont. The bias voltage Vcont is supplied to the bias control unit 111 via the terminal VCONT_IN1 of the high frequency amplification unit 21, and is also supplied to the bias control unit 211 via the terminal VCONT_IN2 of the high frequency amplification unit 21.

  Since the transistor Q4 and the bias control unit 111 and the transistor Q8 and the bias control unit 211 have the same basic circuit configuration and are composed of the same type of circuit elements, they tend to vary in the same direction. . Therefore, as in the HPA module 2, by monitoring the idle current of one of the two amplification circuits, the transistor Q4 and the transistor Q4 are determined by determining a bias voltage common to the two amplification circuits. Variations in the idle current of Q8 can be corrected.

  The magnitude of the collector current Icq1 of the bias control unit 111 proportional to the idle current Icq4 is determined in proportion to the magnitude of the voltage applied to both ends of the resistor Rb1, as shown in the above (Equation 1). Similarly, the magnitude of the collector current Icq5 of the bias controller 211 that is proportional to the idle current Icq8 is determined in proportion to the magnitude of the voltage applied across the resistor Rb2.

  When the voltage at both ends of the resistor Rb1 is smaller than the resistor Rb2, if the bias voltage Vcont is changed, the change rate of the collector current with respect to the amount of change of the bias voltage Vcont is higher for the collector current Icq1 than for the collector current Icq5. growing. That is, in this case, it can be said that the transistor Q4 is more sensitive to the bias voltage Vcont than the transistor Q8. In such a case, if the bias voltage Vcont is adjusted by monitoring the idle current of the transistor Q8, the transistor Q4 is excessively corrected, and the idle current Icq4 may be greatly deviated from the target value. Therefore, when there is a difference in sensitivity of the idle current with respect to the bias voltage Vcont (there is a difference between the voltage at both ends of the resistor Rb2 and the voltage at both ends of the resistor Rb1), as in the HPA module 2 according to the second embodiment. By monitoring the idle current of the transistor having the higher sensitivity to the bias voltage Vcont and adjusting the bias voltage Vcont, variations in characteristics of the high-frequency amplifier 21 can be suppressed with higher accuracy.

  Further, in the HPA module 2, since one regulator unit 101 generates a bias voltage Vcont common to two amplifier circuits, compared with a case where the regulator unit 101 for generating a bias voltage is provided corresponding to each amplifier circuit. Thus, an increase in the chip area of the bias voltage generation unit 10 can be suppressed.

<< Embodiment 3 >>
FIG. 10 is a block diagram showing a circuit configuration of the RF signal transmitting HPA module according to the third embodiment.

  In the second embodiment, the idle current of the transistor Q4 constituting the first stage amplifier circuit is monitored. However, in the HPA module 3 shown in the figure, the idle current of the transistor Q8 constituting the amplifier circuit of the output stage is monitored.

  In addition, the same code | symbol is attached | subjected to the component similar to the HPA modules 1 and 2 among the components which comprise the HPA module 3 in FIG. 10, and the detailed description is abbreviate | omitted.

  In place of the current generator 110 according to the second embodiment, the high-frequency amplifier 31 generates a monitor current Icont2 that monitors the collector current Icq5 (the idle current Icq8 of the transistor Q8) of the transistor Q5A constituting the bias controller 211. A current generator 210 is provided.

  For example, in a two-stage amplifier circuit, when the idle current of the transistor constituting the output stage amplifier circuit is sufficiently large compared to the idle current of the transistor constituting the first stage amplifier circuit, the characteristics of the latter stage amplifier circuit are two stages. This greatly affects the characteristics of the entire amplifier circuit. Therefore, when the idle current Icq8 of the transistor Q8 constituting the output stage amplifier circuit is sufficiently larger than the idle current Icq4 of the transistor Q4 constituting the first stage amplifier circuit, the idle current is large as in the HPA module 3 (transistor By monitoring the idle current of the transistor with the larger emitter size) and adjusting the bias voltage Vcont, variations in the characteristics of the high-frequency amplifier 31 can be suppressed more accurately.

<< Embodiment 4 >>
FIG. 11 is a block diagram showing a circuit configuration of an RF signal transmitting HPA module according to the third embodiment.

  In the second and third embodiments, the bias voltage Vcont generated based on one monitor current Icont1 (or Icont2) is supplied in common to the two amplifier circuits in the first stage and the latter stage, but the HPA module 4 shown in FIG. The bias voltage generated separately based on the monitor current of each amplifier circuit is output to the corresponding amplifier circuit.

  In addition, the same code | symbol is attached | subjected to the component similar to HPA modules 1 thru | or 3 among the components which comprise the HPA module 4 in FIG. 11, and the detailed description is abbreviate | omitted.

  The high frequency amplification unit 41 includes a current generation unit 110 and a current generation unit 210. The monitor current Icont1 of the idle current Icq4 (the collector current Icq1 of the transistor Q1A) of the transistor Q4 generated by the current generator 110 is output via the terminal ICONT_OUT1. On the other hand, the monitor current Icont2 of the idle current Icq8 (the collector current Icq5 of the transistor Q5A) of the transistor Q8 generated by the current generator 210 is output via the terminal ICONT_OUT2. Other circuit blocks are the same as those of the high-frequency amplifiers 11, 21, and 31.

  The bias voltage generation unit 40 determines the magnitude of the monitor current Icont1 of the first-stage amplifier circuit in the high-frequency amplification unit 41, generates the bias voltage Vcont1, and sets the monitor current Icont2 of the output-stage amplifier circuit in the high-frequency amplification unit 41. The magnitude is determined and a bias voltage Vcont2 is generated. Specifically, the bias voltage generation unit 40 determines a monitor current Icont1 and generates a bias voltage Vcont1 as a functional unit, such as a regulator circuit 101_1, a reference voltage generation circuit 102_1, a current-voltage conversion circuit 103_1, and a comparator CMP1. , CMP2, delay circuits 105 and 106, flip-flop circuits FF1 and FF2, and a reset circuit 104_1. The bias voltage generation unit 40 is a functional unit for determining the monitor current Icont2 and generating the bias voltage Vcont2, and includes a regulator circuit 101_2, a reference voltage generation circuit 102_2, a current-voltage conversion circuit 103_2, comparators CMP3, CMP4, Delay circuits 107 and 108, flip-flop circuits FF3 and FF4, and a reset circuit 104_2 are provided. A method for generating the bias voltages Vcont1 and Vcont2 based on the monitor currents Icont1 and Icont2 is the same as that in the first embodiment. The bias voltage Vcont1 is output via the terminal VCONT_OUT1, and is supplied to the bias controller 111 via the terminal VCONT_IN1 of the high frequency amplifier 41. The bias voltage Vcont2 is output via the terminal VCONT_OUT2, and is supplied to the bias controller 211 via the terminal VCONT_IN2 of the high frequency amplifier 41.

  According to the HPA module 4, the idle currents of the transistors of the first stage amplifier circuit and the output stage amplifier circuit are monitored, and the bias voltages Vcont1 and Vcont2 are separately adjusted based on the monitor currents Icont1 and Icont2. The variation is adjusted for each amplifier circuit, and the overall characteristics of the high-frequency amplifier 41 can be adjusted with higher accuracy.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in Embodiments 1 to 4, the power-on reset signal is used as the reset signal RST of the flip-flop circuits FF1 to FF4. However, the present invention is not limited to this. For example, in addition to the power-on reset signal, an externally input reset signal may be used. For example, if initialization of the flip-flop circuits FF1 to FF4 is made possible by a reset signal output from an RFIC, a baseband circuit, or the like, the timing for performing the monitor current determination process is not limited to after the power is turned on. It is also possible to do this.

  In the first to fourth embodiments, the grounded-emitter amplifier circuit is exemplified as the amplifier circuit. However, the present invention is not limited to this, and an amplifier circuit whose characteristics such as gain, efficiency, and linearity change depending on the bias current of the transistor. If there is, the same effect can be expected. In the second to fourth embodiments, the amplifier circuit in the high-frequency amplifiers 21, 31, and 41 is a two-stage amplifier circuit. However, the present invention is not limited to this, and may be a multistage amplifier circuit having three or more stages. In the case of a multistage amplifier circuit having three or more stages, for example, in the second embodiment, the monitor current of the amplification transistor having the highest sensitivity of the idle current to the bias voltage may be generated. In the third embodiment, the idle current is the highest. The monitor current of the amplifying transistor having a large current may be generated.

  In the fourth embodiment, circuit blocks in the bias voltage generation unit 40 may be shared according to the accuracy of variation correction, the required chip area, and the like. For example, the circuit scale may be reduced by sharing the reset circuit 104_1 and the reset circuit 104_2 or by sharing the reference voltage generation circuit 102_1 and the reference voltage generation circuit 102_2.

1-4 HPA module 5 RFIC (signal source)
10 Bias voltage generator (BIAS)
VBATT power supply terminal VCONT_OUT Bias voltage output terminal ICONT_IN Monitor current input terminal 100 Band gap constant voltage circuit 101 Regulator section 102 Reference voltage generation circuit 103 Current voltage conversion circuit 104 Reset circuit (PWR_ON_RST)
105, 106 Delay circuit CMP1, CMP2 Comparator FF1, FF2 Flip-flop circuit Vcont Bias voltage Vs Monitor voltage Vr5, Vr45 Reference voltage Vbgr Output voltage of band gap constant voltage circuit SQ1, SQ2 Output signal of flip-flop circuit 11 High frequency amplifier ( AMP)
VIN power supply terminal VCONT_IN bias voltage input terminal ICONT_OUT monitor current output terminal PIN RF signal input terminal POUT RF signal output terminal 110 current generator 111 bias controller 112 to 114 matching circuit (MCG_CIR)
Q4 Bipolar transistor for amplification L Inductor Rb1, Rbb1 Resistance Q1A, Q1B, Q2, Q3 Bipolar transistor Icq4 Collector current (bias current) of transistor Q4
Icq1 Collector current of transistor Q1A Icont Monitor current I_1, I_2, I_3 Characteristics of collector current Icq1 G_1, G_2, G_3 Gain characteristics A_1, A_2, A_3 Linearity (ACLR1) characteristics 801 to 803 Current range 21 High frequency amplifier 211 Control unit VCONT_IN1, VCONT_IN2 Bias voltage input terminal Icont1 Monitor current 31 High frequency amplification unit 210 Current generation unit Icont2 Monitor current 41 High frequency amplification unit ICONT_OUT1, ICONT_OUT2 Monitor current output terminal 40 Bias voltage generation unit VCONT_OUT1 VCONT_OUT1V Terminals ICONT_IN1, ICONT_IN2 Monitor current input terminals 101_1, 101_2 Reg 102_1, 102_2 Reference voltage generation circuit 103_1, 103_2 Current-voltage conversion circuit 104_1, 104_2 Reset circuit (PWR_ON_RST)
107, 108 Delay circuit CMP3, CMP4 Comparator FF3, FF4 Flip-flop circuit Vcont1, Vcont2 Bias voltage

Claims (10)

A high frequency amplifier for amplifying the power of the input RF signal;
A bias voltage generation unit that generates a bias voltage of the high-frequency amplification unit,
The high-frequency amplifier is
One or more transistors that amplify and output the input RF signal; and
A bias controller that determines a bias state of the transistor based on a bias voltage generated by the bias voltage generator;
A current generator that generates a monitor current proportional to an idle current flowing through the transistor based on the bias voltage;
The bias voltage generation unit performs a determination process for determining which current range is included in a plurality of preset current ranges, and holds a determination result of the determination process, A voltage corresponding to the determination result is generated and output as the bias voltage ,
The determination result is initialized by a power-on reset signal, and held without being updated until the power-on reset signal is next input . The bias voltage generator is
A determination unit for performing the determination process;
And the volatile storage unit that holds the previous Symbol Determination result,
Includes a regulator circuit for generating the bias voltage according to the prior Symbol Determination result, the,
The semiconductor device according to claim 1, wherein the storage unit is initialized by the power-on reset signal. The discrimination unit
A current-voltage converter for converting the monitor current into a voltage;
A plurality of reference voltage generators for generating different reference voltages;
A plurality of comparators provided corresponding to each of the reference voltages, comparing the corresponding reference voltage and the converted voltage, and outputting a comparison result;
The semiconductor device according to claim 2, wherein the storage unit holds a comparison result output from each of the comparators as the determination result . The semiconductor device according to claim 1, wherein the high-frequency amplification unit and the bias voltage generation unit are configured on separate semiconductor substrates . A plurality of the transistors are cascaded,
The high-frequency amplifier has the bias controller and the current generator for each transistor,
The bias voltage generation unit performs the determination processing on the monitor current generated by each current generation unit, and outputs the bias voltage generated according to each determination result to the corresponding bias control unit. Item 14. The semiconductor device according to Item 1 . A plurality of the transistors are cascaded,
The high-frequency amplifier has the bias controller for each transistor,
The current generator generates the monitor current related to any one of the plurality of transistors,
The semiconductor device according to claim 1, wherein the bias voltage generation unit outputs the generated voltage to each of the bias control units as a common bias voltage . The semiconductor device according to claim 6, wherein the one transistor is a transistor having a change rate of the idle current with respect to a change of the bias voltage among the plurality of transistors . The semiconductor device according to claim 6, wherein the one transistor is a transistor having the largest idle current among the plurality of transistors . A high frequency amplifier for amplifying the power of the input RF signal;
A bias voltage generation unit that generates a bias voltage of the high-frequency amplification unit,
The high-frequency amplifier is
One or more first transistors for amplifying and outputting an input RF signal; and
A bias controller that determines a bias state of the first transistor based on a bias voltage generated by the bias voltage generator;
A current generation unit that generates a monitor current proportional to an idle current flowing through the first transistor;
The current generation unit includes a diode-connected second transistor, a third transistor constituting one of the current mirror circuits connected in series with the second transistor, and a fourth transistor constituting the other of the current mirror circuit, And supplying the monitor current from the fourth transistor to the bias voltage generator,
The bias voltage generation unit performs a determination process for determining which current range is included in a plurality of preset current ranges, and holds a determination result of the determination process, A voltage corresponding to the determination result is generated and output as the bias voltage,
The determination result is initialized by a power-on reset signal, and held without being updated until the power-on reset signal is next input . A high frequency amplifier for amplifying the power of the input RF signal;
A bias voltage generation unit that generates a bias voltage of the high-frequency amplification unit,
The high-frequency amplifier is
One or more transistors that amplify and output the input RF signal; and
A bias controller that determines a bias state of the transistor based on a bias voltage generated by the bias voltage generator;
A current generation unit that generates a monitor current proportional to an idle current flowing in the transistor,
The bias voltage generation unit is reset only by a power-on reset signal and a plurality of comparators for determining which current range of a plurality of preset current ranges is included in the plurality of current ranges. A plurality of set reset flip-flops set based on the comparison results of the comparators, and a voltage corresponding to the determined current range based on the outputs of the plurality of set reset flip-flops, as the bias voltage Output semiconductor device.

Images