KR100318448B1 - A reference voltage generating circuit in semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor circuit technology, and more particularly, to a reference voltage generating circuit of a semiconductor device, and an object thereof is to provide a reference voltage generating circuit of a semiconductor device having a low rate of change of the reference voltage with respect to temperature. The voltage across the diode known to have a negative primary temperature coefficient or the base-emitter voltage Vbe of the bipolar transistor not only has a negative primary temperature coefficient but also a negative secondary temperature coefficient. The present invention further connects the voltage having the positive secondary temperature coefficient in addition to the voltage having the positive primary temperature coefficient so that both the primary and secondary components of the overall temperature coefficient become zero. That is, the present invention enables the generation of a more precise reference voltage than the existing bandgap reference voltage generator having a negative secondary temperature coefficient by zeroing the secondary temperature coefficient.

Description

A reference voltage generating circuit in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor circuit technology, and more particularly, to a reference voltage generation circuit for semiconductor devices.

The reference voltage generator is a circuit that continuously outputs a signal having a constant electric potential. It is an analog to digital converter (ADC), a digital to analog converter (DAC), a phase locked loop (PLL). ), Voltage regulator, DC-to-DC converter, battery controller, etc. are used to generate the reference voltage. Various proposals have been made according to the method of generating the reference voltage, and among them, a bandgap reference voltage generator having a low temperature coefficient is widely used in a technical field requiring a precise reference voltage.

The bandgap reference generator generates a voltage with a negative primary temperature coefficient (e.g., a voltage across the diode or between the base-emitter of a bipolar transistor (BJT)) and a positive primary temperature coefficient. By connecting in series, the mutual temperature coefficients cancel each other out so that the primary temperature coefficient becomes substantially zero. Thus, it is to reduce the change of the reference voltage with respect to temperature.

However, in this bandgap reference generator, the primary temperature coefficient is canceled out, but the secondary voltage coefficient of the diode voltage or the base-emitter voltage (Vbe) of the BJT still remains, so that the generated reference voltage The dependence of the curvature shape (usually on a parabolic shape) with respect to. Although the reference voltage has such a form of curvature dependence on temperature, it is possible to generate a reference voltage having a variation error of 20 ppm / ° C or less depending on the degree of matching of each component of the bandgap reference voltage generator. However, it is necessary to lower the rate of change with respect to the temperature of the reference voltage generated as the semiconductor device is highly integrated and high precision to 5 ppm / 占 폚 or less.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a reference voltage generating circuit of a semiconductor device having a low rate of change of the reference voltage with respect to temperature.

1 is a block diagram of a reference voltage generation circuit according to an embodiment of the present invention.

FIG. 2 is an exemplary view of the bandgap reference voltage generator 100 shown in FIG. 1.

3 is an exemplary diagram of the scaling reference voltage generator 200 shown in FIG. 1.

4 is an exemplary view of the reference voltage adjusting / adding unit 300 shown in FIG. 1.

5 is a view showing the bandgap reference voltage generator 100, the scaling reference voltage generator 200, and the reference voltage adjuster / adder 300 shown in FIGS.

6 is a circuit diagram illustrating a reference voltage generation circuit of a semiconductor device according to another embodiment of the present invention.

7 is a circuit diagram illustrating a reference voltage generation circuit of a semiconductor device according to still another embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

100... Band gap reference voltage generator

200... Reference voltage generator for scaling

300... Reference voltage adjustment / addition unit

A2, A4, A12, A14, A22, A24... Operational amplifier

In order to achieve the above object, according to an aspect of the present invention, a bandgap reference voltage generator for generating a first preliminary reference voltage having a primary temperature coefficient adjusted to substantially zero and having a negative secondary temperature coefficient; A scaling reference voltage generator for adjusting a primary temperature coefficient to substantially zero and generating a second preliminary reference voltage having a positive secondary temperature coefficient; And a reference voltage adjusting / adding unit configured to scale and add the first preliminary reference voltage and the second preliminary reference voltage to output a reference voltage having a second temperature coefficient of substantially zero. do.

Further, according to another aspect of the invention, the first and second branches coupled in parallel between the power supply voltage (VDD) and the ground (VSS) and each comprising an emitter-collector path of the bipolar transistor, and the first A bandgap reference voltage generator having an operational amplifier configured to amplify a voltage difference between a first node in a branch and a second node in a second branch to control a current flowing through the first and second branches; A third branch connected in parallel with the first and second branches, wherein the third branch is configured to control the current flowing by the operational amplifier and include the voltage of the third node included therein in the first and second branches. Applied to the base of bipolar transistors; Including a reference voltage output terminal drawn from any one of the nodes included in the first branch, the voltage by the bandgap reference voltage generator and the voltage by the third node is added to the secondary temperature coefficient is substantially A reference voltage generator circuit for a semiconductor device is provided so as to be output as a zero reference voltage.

Further, according to another aspect of the invention, the first and second branches coupled in parallel between the power supply voltage (VDD) and the ground (VSS) and each comprising an emitter-collector path of a bipolar transistor, A bandgap reference voltage generator including an operational amplifier configured to amplify a voltage difference between a first node in a first branch and a second node in a second branch to control a current flowing through the first and second branches; A reference voltage generating circuit of a semiconductor device is provided having a scaling load coupled between a base of the bipolar transistors and a ground to output a reference voltage having a substantially zero secondary temperature coefficient.

The voltage across the diode known to have a negative primary temperature coefficient or the base-emitter voltage Vbe of the bipolar transistor not only has a negative primary temperature coefficient but also a negative secondary temperature coefficient. The present invention further connects the voltage having the positive secondary temperature coefficient in addition to the voltage having the positive primary temperature coefficient so that both the primary and secondary components of the overall temperature coefficient become zero. That is, the present invention enables the generation of a more precise reference voltage than the existing bandgap reference voltage generator having a negative secondary temperature coefficient by zeroing the secondary temperature coefficient.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

1 is a block diagram of a reference voltage generation circuit according to an embodiment of the present invention, which will be described below with reference to the drawing.

Referring to FIG. 1, the reference voltage generator circuit includes a bandgap reference voltage generator 100, a scaling reference voltage generator 200, and a reference voltage adjuster / adder 300. The bandgap reference voltage generator 100 generates a first preliminary reference voltage VN having a primary temperature coefficient of zero but having a negative secondary temperature coefficient. The scaling reference voltage generator 200 generates a second preliminary reference voltage VP having a primary temperature coefficient of zero but having a positive secondary temperature coefficient. The reference voltage adjusting / adding unit 300 includes a first preliminary reference. The reference voltage VREF having a desired magnitude is output by adjusting and adding the magnitudes of the reference voltage VN and the second preliminary reference voltage VP.

FIG. 2 illustrates a detailed circuit of the bandgap reference voltage generator 100 of FIG. 1. Referring to this, the bandgap reference voltage generator 100 may include PMOS transistors P2 and P4 and a resistor ( R2, R4, R6, PNP bipolar transistors Q2, Q4 and operational amplifier A2. The drain-source path of the PMOS transistor P2, the resistors R2 and R6, and the emitter-collector path of the bipolar transistor Q2 are connected in series between the power supply voltage VDD and ground VSS so that one branch form a branch, and the drain-source path of PMOS transistor P4, the resistor R4 and the emitter-collector path of bipolar transistor Q4 are connected in series between power supply voltage VDD and ground VSS. Are connected to form another branch, and the bases of the bipolar transistors Q2 and Q4 are coupled to ground VSS. In addition, the potential difference between the nodes X1 and X2 is amplified and fed back through the operational amplifier A2 to control the switching of the PMOS transistors P2 and P4. Thus, the current flowing through each branch is controlled by the output of the operational amplifier.

In the bandgap reference voltage generator 100 having such a configuration, the primary temperature coefficient may be zero by adjusting the resistance values of the three resistors R2, R4, and R6. That is, by adjusting the magnitudes of the voltages applied to the positive input terminal and the negative input terminal of the operational amplifier, the primary temperature coefficient of the first preliminary reference voltage VN, which is the output of the bandgap reference voltage generator 100, is zero (0). You can do However, in the bandgap reference voltage generator 100 having such a configuration, the first preliminary reference voltage VN is always negative due to the characteristics of the base-emitter voltage Vbe of the PNP bipolar transistors Q2 and Q4. It has a secondary temperature coefficient of. Therefore, the first preliminary reference voltage VN generated only by the bandgap reference voltage generator 100 exhibits a temperature characteristic of the curvature form as described above.

3 illustrates a detailed circuit of the scaling reference voltage generator 200 of FIG. 1. Referring to this, the scaling reference voltage generator 200 includes PMOS transistors P12, P14, and P16 and a resistor R12. And R14, R16, R18, and R20, operational amplifiers A12 and A14, and bipolar transistors Q12 and Q14. The bipolar transistors Q12 and Q14 may be configured as PNP bipolar transistors. The drain-source path and the resistors R18 and R20 of the PMOS transistor P12 are connected in series between the power supply voltage VDD and the ground VSS to form one branch, and the PMOS transistor P14 The drain-source path, resistor R12, and emitter-collector path of the PNP bipolar transistor Q12 are connected in series between the supply voltage VDD and ground VSS to form another branch. The drain-source path of the MOS transistor P16, the resistors R14 and R16, and the emitter-collector path of the PNP bipolar transistor Q14 are connected in series between the power supply voltage VDD and ground VSS. It forms one branch. Further, the potential difference between the nodes X3 and X4 is amplified and fed back through the operational amplifier A12 to control the switching of the PMOS transistors P14 and P16, and the potential difference between the nodes X3 and X5 is the operational amplifier A14. It is amplified by to control the switching of the PMOS transistor (P12). That is, the current flowing through each branch is controlled by the output of the op amp. The second preliminary reference voltage VP, which is an output of the scaling reference voltage generator 200, is output from a connection node between the PMOS transistor P16 and the resistor R14. In the scaling reference voltage generator 200, the primary temperature coefficient of the second preliminary reference voltage VP is zero by adjusting the resistance values of the resistors R12, R14, R16, R18, and R20. In this way, the second preliminary reference voltage VP, which is the output of the scaling reference voltage generator 200, outputs a voltage whose primary temperature coefficient is zero and the secondary temperature coefficient is positive. That is, as the temperature increases, the second preliminary reference voltage VP, which is an output in proportion to its square, increases.

FIG. 4 illustrates a detailed circuit of the reference voltage adjuster / adder 300 of FIG. 1. The reference voltage adjuster / adder 300 includes a first preliminary reference voltage VN and a second preliminary reference voltage VP. Add and adjust the size of. Since the first preliminary reference voltage VN and the second preliminary reference voltage VP both have a first temperature coefficient of zero, the first temperature coefficient is always zero even if the magnitude is adjusted and added. Therefore, when the size is adjusted and added so that the secondary temperature coefficients cancel each other, both the primary temperature coefficient and the secondary temperature coefficient become zero in the final reference voltage VREF.

Meanwhile, the reference voltage adjusting / adding unit 300 includes PMOS transistors P22, P24, P26, and P28, NMOS transistors N22 and N24, operational amplifiers A22 and A24, and resistors R22, R24, and R26. It is configured to include. The first preliminary reference voltage VN is converted into the first preliminary current IN by a voltage to current converter composed of an operational amplifier A22 and a resistor R26. Similarly, the second preliminary reference voltage VP is converted into the second preliminary current IP by a voltage to current converter composed of an operational amplifier A24 and a resistor R22. Here, scaling may be performed by adjusting the resistance values of the resistors R26 and R22. The value of the first preliminary current IN may be represented by Equation 1 below, and the value of the second preliminary current IP may be represented by Equation 2 below.

IN = VN / R26

VN = VP / R22

In addition, the first preliminary current IN is output by a current mirror composed of PMOS transistors P22 and P24, and the second preliminary current IP is output by a current mirror composed of PMOS transistors P26 and P28. (I.e. branch with resistor R24) added and added. Therefore, the output current Iout flowing through the resistor R24 becomes the sum of the first preliminary current IN and the second preliminary current IP, that is, Iout = IN + IP. In addition, the output reference voltage VREF may be represented as a product of the output current Iout and the resistor R24. Thus, the output reference voltage VREF can be expressed as Equation 3 below.

As such, the resistance values of the resistors R24, R22, and R26 are adjusted to cancel the secondary temperature coefficients of the first preliminary reference voltage VN and the second preliminary reference voltage VP. Thus, the final output reference voltage VREF is zero for both the primary temperature coefficient and the secondary temperature coefficient, so that it is possible to generate a stable reference voltage almost unchanged with the temperature change.

5 is a view showing the bandgap reference voltage generator 100, the scaling reference voltage generator 200, and the reference voltage adjuster / adder 300 shown in FIGS. It shows the connection relationship.

6 is a circuit diagram illustrating a reference voltage generation circuit of a semiconductor device in accordance with another embodiment of the present invention.

Referring to FIG. 6, the reference voltage generator circuit of the semiconductor device includes a bandgap reference voltage generator 100 and a secondary temperature coefficient controller 400. The secondary temperature coefficient controller 400 includes a PMOS transistor P32 and a resistor R32. The drain-source path and the resistor R32 of the PMOS transistor P32 are coupled in series between the power supply voltage VDD and the ground VSS. The coupling point node X5 of the PMOS transistor P32 and the resistor R32 is coupled to the bases of the PNP bipolar transistors Q32 and Q34 of the bandgap reference voltage generator 100.

In such a circuit, the temperature characteristic of the voltage of the node X5 is determined by the temperature characteristic of the current gain of the bipolar transistors Q32 and Q34. By the way, the temperature characteristic of this current gain has both a primary temperature coefficient and a secondary temperature coefficient having a positive value. In addition, since the voltage of the node X5 is added to the first preliminary reference voltage VN, which is an output when only the bandgap reference voltage generator 100 is configured, the output reference voltage VREF may zero the secondary temperature coefficient. Will be.

7 is a circuit diagram illustrating a reference voltage generation circuit of a semiconductor device in accordance with still another embodiment of the present invention.

Referring to FIG. 7, the reference voltage generator circuit includes a bandgap reference voltage generator 100 and a secondary temperature coefficient controller 500, and the secondary temperature coefficient controller 500 includes a resistor R40. It is. The resistor R42 is coupled between the node X6 and the ground VSS, and the node X6 is coupled to the bases of the PNP bipolar transistors Q2 and Q4 of the bandgap reference voltage generator 100. As in FIG. 6, the voltage of the node X6 has a positive value of both the primary and secondary temperature coefficients, and this voltage is a first preliminary reference which is an output when only the existing bandgap reference voltage generator 100 is configured. It is added to the voltage VN to become the final output reference voltage VREF. Therefore, the secondary temperature coefficient of the reference voltage VREF can be adjusted to zero.

6 and 7, although the primary temperature coefficient components of the nodes X5 and X6 of the secondary temperature coefficient controllers 400 and 500 are not adjusted to zero, they are not very large. However, since a small amount of primary temperature coefficient components may be reflected in the reference voltage VREF, the required chip area is smaller than that of the reference voltage generation circuit shown in FIG. 5, but the stability to temperature is somewhat lower.

The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention.

As described above, the reference voltage generating circuit of the present invention not only zeroes the primary temperature coefficient but also zeros the secondary temperature coefficient, so that the rate of change of the generated reference voltage with respect to temperature is very low. have. Thus, there is an advantage in increasing the operation precision of analog related circuits in semiconductor devices such as analog / digital converters, voltage regulators, DC-to-DC converters and the like. In particular, in the ADC / DAC with a built-in reference voltage generator circuit, the precision and stability of the reference voltage determine the performance of the entire chip. In particular, if an ADC or a DAC is implemented using a simple bandgap reference voltage generator circuit in which only the primary temperature coefficient is zero-corrected, practically, an ADC / DAC design of 12 bits or more is impossible. However, in the case of using the reference voltage generator circuit corrected to zero up to the secondary temperature coefficient as proposed in the present invention, an ADC / DAC design of 12 bits or more is possible. In addition, since the reference voltage generator circuit of the semiconductor device proposed in the present invention can be produced by a single chip, it has an advantage of improving the performance of a system using the same. For example, when employed in digitized voltmeters, ammeters, as well as oscilloscopes, pulse / signal generators, there is an advantage that can significantly improve the performance of the system.

Claims (10)

A bandgap reference voltage generator for generating a first preliminary reference voltage having a primary temperature coefficient adjusted to substantially zero and having a negative secondary temperature coefficient; A scaling reference voltage generator for adjusting a primary temperature coefficient to substantially zero and generating a second preliminary reference voltage having a positive secondary temperature coefficient; And A reference voltage adjusting / adding unit configured to scale and add the first preliminary reference voltage and the second preliminary reference voltage to output a reference voltage having a second temperature coefficient of substantially zero; A reference voltage generation circuit of a semiconductor device having a. The method of claim 1, The scaling reference voltage generator, A first branch, a second branch, and a third branch connected in parallel between the power supply voltage VDD and ground, wherein the first branch and the second branch include bipolar transistors; A first operational amplifier configured to control a current flowing in the first branch and the second branch by amplifying a voltage difference between the first node included in the first branch and the second node included in the second branch; And A second operational amplifier configured to control a current flowing in a third branch by amplifying a voltage difference between the second node and a third node included in the third branch, And a second preliminary reference voltage is output from any one of the nodes included in the first branch. The method of claim 2, The first branch comprises a first PMOS transistor, a first resistor and a second resistor, and a first PNP bipolar transistor coupled in series between the power supply voltage VDD and ground—the collector of the first PNP bipolar transistor. Is grounded; The second branch includes a second PMOS transistor, a third resistor, and a second PNP bipolar transistor coupled in series between the power supply voltage VDD and ground VSS, wherein the collector of the second PNP bipolar transistor is Grounded; The third branch includes a third PMOS transistor, a fourth resistor and a fifth resistor coupled in series between the power supply voltage VDD and the ground VSS; The first input terminal of the first operational amplifier is connected to a coupling point of the first resistor and the second resistor and the second input terminal is coupled to the emitter of the third resistor and the second PNP bipolar transistor and outputs the same. Is coupled to gates of the first PMOS transistor and the second PMOS transistor; A first input terminal of the second operational amplifier is coupled to a coupling point of a fourth resistor and a fifth resistor, a second input terminal is connected to an emitter of the second PNP bipolar transistor, and an output terminal of the second operational amplifier is A reference voltage generation circuit of a semiconductor device, characterized in that coupled to the gate of the MOS transistor. The method of claim 1, The reference voltage adjusting / adding unit. A first voltage-to-current converter that scales the first preliminary reference voltage and converts the first preliminary reference voltage into a first preliminary current; A second voltage-current converter for scaling the second preliminary reference voltage and converting the second preliminary reference voltage into a second preliminary current; An output branch through which output current flows and including at least one load element; A first current mirror for transferring the first preliminary current to the output branch; And A second current mirror for delivering said second preliminary current to said output branch, And the first preliminary current and the second preliminary current are added to the output branch so as to flow so as to output a voltage applied to the output load as a reference voltage (VREF). The method of claim 4, wherein Each of the first and second voltage-to-current converters includes an operational amplifier that scales a voltage of a branch through which the converted preliminary current flows and inputs it to a second input terminal, and inputs a corresponding preliminary voltage to the first input terminal. A reference voltage generation circuit of a semiconductor device, characterized in that. The method of claim 5, The reference voltage adjusting / adding unit is And an NMOS transistor gated by an output of the operational amplifier corresponding to a branch through which the first and second preliminary currents flow. The method of claim 1, The bandgap reference voltage generator, First and second branches coupled in parallel between power supply voltage VDD and ground VSS, each including an emitter-collector path of a bipolar transistor; And an operational amplifier configured to amplify the voltage difference between the first node in the first branch and the second node in the second branch to control the current flowing through the first and second branches. Generation circuit. First and second branches coupled in parallel between power supply voltage VDD and ground VSS, each comprising an emitter-collector path of a bipolar transistor, and a first node and a second branch within the first branch. A bandgap reference voltage generator including an operational amplifier for amplifying a voltage difference between a second node and controlling a current flowing through the first and second branches; A third branch connected in parallel with the first and second branches, wherein the third branch is configured to control the current flowing by the operational amplifier and include the voltage of the third node included therein in the first and second branches. Applied to the base of bipolar transistors; Including a reference voltage output terminal drawn from any one of the nodes included in the first branch, And the voltage generated by the bandgap reference voltage generator and the voltage generated by the third node are added so that the secondary temperature coefficient is output as a reference voltage having a substantially zero value. The method of claim 8, The third branch, A PMOS transistor having a drain connected to the power supply voltage VDD and having a gate coupled to an output of the operational amplifier; A resistor coupled between the source of the PMOS transistor and the ground (VSS), And a source of the PMOS transistor is connected to a base of a bipolar transistor included in the bandgap reference voltage generator as the third node. First and second branches coupled in parallel between power supply voltage VDD and ground VSS, each comprising an emitter-collector path of a bipolar transistor, and a first node and a second branch within the first branch. A bandgap reference voltage generator including an operational amplifier for amplifying a voltage difference between a second node and controlling a current flowing through the first and second branches; A scaling load coupled between the base and ground of the bipolar transistors, A reference voltage generating circuit of a semiconductor device, characterized in that for outputting a reference voltage having a substantially zero secondary temperature coefficient.