JP3517766B2 - RF power amplifier circuit and mobile communication terminal device - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an RF for wireless communication.
The present invention relates to a technology effectively applied to an RF power amplifier circuit using a power amplifier circuit, and further a GaAs FET (field effect transistor), and relates to a digital system using a CDMA (code division multidimensional connection) technology, for example. The present invention relates to a technology effectively used for a mobile phone terminal.

[0002]

2. Description of the Related Art In a mobile communication terminal device such as a mobile phone terminal, in order to transmit a radio signal in a microwave region of 1 GHz or more, a depletion type GaAs F having a faster operation speed than a conventional silicon bipolar transistor is used.
An RF amplification power amplification circuit adopting ET is used.

As a communication system, a so-called CDMA technique, which is a code division multiple access system for performing spread spectrum, has been attracting attention in place of the conventional frequency division multiple access system or time division multiple access system in order to improve frequency utilization efficiency. ing.

In this type of mobile communication terminal device, first,
In order to enhance portability, it is required to be small and lightweight, consume less power, and have a long battery life. At the same time, no adjustment is required to improve the productivity and the stability of operation.

Also, a cellular type mobile phone system,
Particularly in a CDMA system, it is very effective to suppress the transmission power to a necessary minimum in order to improve frequency utilization efficiency. That is, by reducing the transmission power when the terminal station is in the immediate vicinity of the base station and increasing the transmission power when the terminal station is far from the base station, it is possible to suppress the noise level that interferes with CDMA demodulation.

For this purpose, the transmission power should be controlled finely. The control of the transmission power may be performed by controlling the input level of the RF power amplifier circuit and using a linear RF power amplifier circuit that exhibits good linearity over a very wide output range of 0.02 mW to 200 mW. A CDMA mobile communication terminal device uses a linear operation RF power amplifier circuit that is biased so as to operate linearly even at maximum output.

Regarding the mobile communication terminal device, for example, "Nikkei Electronics 199" published by Nikkei BP, Inc.
The outline is described in the January 13, 1995 issue (no. 680), pp. 65-90 (special feature: mobile phones).

[0008]

However, the present inventors have clarified that the above-mentioned technique has the following problems.

That is, the bias current of the linear amplifier circuit is constant regardless of the output. Therefore, the linear RF power amplifier circuit, which is biased to operate linearly at the maximum output, always has the bias current at the maximum output even when the transmission power is much lower than the maximum output, that is, at the low power output. Keep flowing. This is a waste of power consumption. Therefore, it is considered to reduce the bias current when the transmission power is low.

However, the FE that constitutes the RF power amplifier circuit
The characteristic of T is not always constant and varies depending on various conditions such as the manufacturing process and mounting. Therefore, when setting the bias current, it is necessary to set the bias accurately for each product or to set the bias with a sufficient variation margin for the transmission power.

However, in the former case, since it is necessary to make troublesome adjustments for each product, there arises a problem that productivity is markedly reduced. In the latter case, a large bias current must be passed in order to have a sufficient margin for the transmission output, which causes a problem of increasing the power consumption and shortening the battery life.

A technique for supplying the bias voltage without adjustment is, for example, IEEE Trans. Cir
cut Theory, vol. CT-12, pp.
586-590, Dec. As described in 1965, a bias circuit using the collector voltage / current characteristic of a silicon bipolar transistor is known. However, the bias circuit disclosed therein utilizes characteristics peculiar to a silicon bipolar transistor (collector voltage / current characteristics, base-emitter voltage, etc.) and cannot be applied to FETs. Made clear by the men.

The object of the present invention is effective in reducing the size and weight of a mobile communication terminal device using a radio signal in the microwave region of 1 GHz or more and operating for a long time with a battery, and the productivity is remarkably reduced. It is an object of the present invention to provide a technique that enables stable and efficient RF power amplification even under the use condition of a single power supply without requiring individual adjustment.

The above and other objects and features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

[0015]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the first FET forming the RF power amplifier circuit by the source grounding and depletion operation.
At the same time, a second FET that is the same kind of FET as the first FET and has the same channel length and a small channel width, and the first FET that generates a negative voltage from the positive power supply voltage. And a variable voltage generation circuit that distributes a negative bias voltage to each gate of the second FET, and a negative feedback circuit that controls the variable voltage generation circuit so that the drain current of the second FET becomes a predetermined set value. The bias of the RF power amplifier circuit is set by the operation of the negative feedback circuit.

According to the above-mentioned means, even if the characteristics of the FETs forming the RF power amplifier circuit vary due to various conditions such as the manufacturing process or mounting, the FETs are different.
It is possible to set the bias voltage necessary for performing the predetermined amplification operation with high efficiency in a self-aligning manner with good reproducibility without adjustment.

This is effective for reducing the size and weight of a mobile communication terminal device that uses a radio signal in the microwave region of 1 GHz or more and for operating for a long time on a battery, and at the same time, reduces the suitability for production. The objective is achieved of enabling stable and efficient RF power amplification even under conditions of use of a single power supply, without the need for adjustment.

[0019]

The invention according to claim 1 of the embodiment of the present invention includes a first FET to perform RF power amplifier by a source grounded depletion operation (J1, J2), said first FET (J1, J2 ) And a second F formed with the same channel length and a small channel width.
ET (Jx), drain voltage of the second FET and reference
Voltage comparison circuit (16) that amplifies and outputs the difference from the voltage
If, based on the output of the voltage comparator circuit, and generates a negative voltage from the positive supply voltage said first FET (J1, J2) and <br/> second negative bias voltage to the gates of the FET (Jx) (V
a variable voltage generator circuit that distributes o) (17), said first
Between the gate of the FET and the output side of the variable voltage generating circuit
A first resistor (R1, R2) connected in series between
Output of the gate of the second FET and the variable voltage generating circuit
A second resistor (Rx) connected in series between the
The output voltage of the variable voltage generating circuit is controlled by the second FET.
To the bias voltage via the second resistor in series
The drain voltage becomes equal to the reference voltage.
Such feedback control is performed by using the gate of the first FET and the gate of the first FET.
The gates of the two FETs were cut off from each other in an alternating manner.
The negative feedback circuit (1) that controls the variable voltage generating circuit (17) so that the drain current (Ix) of the second FET (Jx) becomes a predetermined set value by performing the operation in this state.
And 8) and forming the negative feedback circuit.
The output voltage of the variable voltage generating circuit is the gate of the first FET.
As a bias voltage via the above first resistor in series
Is configured to be given by
It is effective in reducing the size and weight of mobile communication terminal devices such as mobile phone terminals and operating for a long time with batteries, and under the condition of using a single power supply without the need for individual adjustment that significantly reduces productivity. However, it is possible to obtain the effect of enabling stable and efficient RF power amplification.

The invention described in claim 2 is characterized in that, in addition to the structure described in claim 1, the first FET (J1, J2) forms a linear amplifier circuit. For example, it is possible to obtain the effect that the power amplification characteristic suitable for the communication of the CDMA system can be secured.

According to the invention described in claim 3, in addition to the invention described in claim 1 or 2, the first FET (J1, J2) is provided.
And the second FET (Jx) are formed on the same semiconductor chip in a thermally coupled state.
The similar relationship between the ET (J1, J2) and the second FET (Jx) becomes closer to each other, and the effect of further improving the accuracy of bias setting is obtained.

The invention described in claim 4 is the invention according to claims 1 to 3.
And the drain current (Ix) of the second FET (Jx) controlled by the negative feedback circuit (18).
This is provided with a variable setting circuit that sets the value according to a signal from the outside (60), and this has the effect that the bias condition of the RF power amplifier circuit can be finely set from the outside (60). To be

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

[0033] The invention of claim 5 includes a first FET to perform RF power amplifier by a source grounded depletion operation (J1, J2), said first FET (J1, J
A second FET (Jx) which is of the same type as 2) and has the same channel length and a small channel width;
Increase the difference between the drain voltage of the second FET and the reference voltage.
And a voltage comparison circuit (16) for outputting in a wide range and the voltage comparison circuit (16).
Based on the output of the road, above the positive supply voltage to generate a negative voltage
Serial first FET (J1, J2) and a second FET (J
x), a variable voltage generating circuit (17) for distributing a negative bias voltage (Vo) to each gate, and the gate of the first FET
Connected in series between the output side of the
Of the first resistor (R1, R2) and the second FET
In series between the gate and the output side of the variable voltage generation circuit
The connected second resistor (Rx) and the variable voltage generating circuit
The output voltage of the path to the gate of the second FET
Apply a resistor as a bias voltage through the series and
Feedback control so that the in-voltage becomes equal to the above reference voltage
The gate of the first FET and the gate of the second FET.
Be sure to carry out with the terminals isolated from each other.
And by, with the second drain current of FET (Jx) (Ix) has a negative feedback circuit (18) for controlling the variable voltage generating circuit (17) to a predetermined setting value, the negative Variable voltage generation that forms a feedback circuit
The output voltage of the circuit is the gate of the first FET
It is given as a bias voltage through the resistance of
The control means (50, 60) for variably controlling the set value in accordance with the transmission output is provided , whereby the size and weight of the mobile communication terminal device such as a mobile phone terminal can be reduced. With this, it is possible to achieve a long-time operation with a battery and to improve the production suitability without requiring individual adjustment.

[0034]

[0035]

[0036]

[0037]

[0038]

[0039]

Preferred embodiments of the present invention will be described below with reference to the drawings.

In the figures, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows a schematic configuration of a mobile communication terminal device to which the technique of the present invention is applied.

The mobile communication terminal device shown in FIG.
Configured as a mobile phone terminal according to the method, an RF power amplification circuit 10, an output matching circuit 13, and an RF reception preamplifier 2
0, duplexer (or antenna switching device) 31, wireless transmission / reception antenna 32, transmission side frequency conversion circuit (upverter)
41, a reception side frequency conversion circuit (downverter) 42, a frequency synthesis circuit 4 for generating a local signal for frequency conversion
3, a baseband unit 50 including a transmission / reception IF unit and various control signal transmission / reception functions, a logic control unit 60,
It has an operation panel 61 including an operation unit and a display unit, a headset 62 including a transmitter and a receiver, a built-in battery 70 for supplying an operating power supply (Vdd) of the entire apparatus, and the like.

Here, the entire apparatus is constructed so as to be operated by the positive voltage power source (Vdd) supplied from the built-in battery 70.

The RF power amplifier circuit 10 has a multi-stage structure of a front stage 12 and a final stage 11, and each of the amplification stages 11 and 12 is a junction type GaAs-FET that performs depletion operation.
It is configured using J1 and J2.

The FETs J1 and J2 of the amplification stages 11 and 12 respectively form a source-grounded linear amplification circuit, and perform a linear amplification operation with the gate bias voltage (Vo) distributed from the common bias generation circuit 14. While being biased, the frequency conversion circuit 41 power-amplifies the radio signal Rin converted into a predetermined transmission frequency with a constant gain.

Resistors Rx, R1 and R2 are respectively provided in series in the gate bias voltage supply paths of the FETs Jx, J1 and J2, and the resistors Rx, R1 and R are also provided.
A capacitor Cp is inserted in parallel between 2 and the variable voltage generator 17. Thereby, each FET Jx, J1, J2
The gates of the FETs are blocked (decoupled) from each other in an alternating current (high frequency) manner to prevent the wraparound interference in the FETs.

Depending on the type of FET, each FET Jx,
In some cases, there is a gate leak in J1 and J2, and the voltage drop across the resistors Rx, R1 and R2 due to the gate leak cannot be ignored. In such a case, the resistance value ratio of R1 and Rx is set to be the reciprocal of the channel width ratio of FET J1 and Jx, and similarly, the resistance value ratio of R2 and Rx is FE.
By setting the reciprocal of the channel width ratio of TJ2 and Jx, it is possible to cancel the influence of the gate leak.

The bias generation circuit 14 is composed of a FET Jx, a variable setting circuit 15, a voltage comparison circuit 16, a variable voltage generation circuit 17, a capacitance element C1, a resistor R3 and the like.

The FET Jx is a dummy FET for generating a bias. The dummy FET Jx is a FET of the same type formed on the same semiconductor chip in a thermally coupled state with respect to the FETs J1 and J2 that perform RF power amplification,
The channel length is the same and the channel width is small.

The resistor R3 is connected between the drain of the dummy FET Jx and the power supply potential Vdd to form a drain load. A voltage Vx (= R3 × Ix) corresponding to the drain current Ix of the dummy FET Jx appears at both ends of the resistor R3. That is, the resistor R3 converts the drain current Ix of the dummy FET Jx into a voltage.

The variable setting circuit 15 is a variable voltage source 1 whose output voltage Vr is electrically variably set by a signal from the outside.
It is configured using 51. The output voltage Vr of the variable voltage source 151 is variably set by the digital control signal generated by the logic control unit 60 according to the transmission power.

The voltage comparison circuit 16 is constructed by using an operational amplifier having a sufficiently large amplification gain, and is a dummy FET.
The drain voltage Vx of Jx is compared with the output voltage Vr of the variable voltage source 151, and the difference is amplified and output. The output of the voltage comparison circuit 16 is given to the variable voltage generation circuit 17 as a control signal.

The variable voltage generating circuit 17 has a positive power supply voltage (V
It is a circuit that generates a negative voltage (Vo) from dd), and is configured such that the output voltage Vo is variably controlled by the output of the comparison circuit 16. The capacitive element C1 smoothes (converts to DC) the output voltage Vo of the bias generation circuit 17.

The output voltage Vo is applied as a bias voltage to the gate of the dummy FET Jx via the resistor Rx in series. Thereby, the drain current Ix is a set value (Vr) given by the variable voltage source 151.
DC negative feedback control is performed so as to be equal to. That is, the FET Jx, the variable setting circuit 15,
Voltage comparison circuit 16, variable voltage generation circuit 17, capacitance element C
1. The resistance R3 is the drain current Ix of the dummy FET Jx.
Forms a negative feedback circuit 18 that variably controls the bias voltage (Vo) so that the voltage becomes a predetermined set value (Vdd-R3 × Ix = Vr).

Although not shown in detail, the baseband unit 50 has a function of generating and receiving / demodulating a radio transmission signal of the CDMA system, a detecting means for detecting the electric field strength level of the radio reception signal, and / or Alternatively, it has a built-in receiving means for acquiring the electric field strength information of the radio wave transmitted by the local station which is fed back from the radio communication partner station.

Although not shown in detail in the figure, the logic control unit 60 has, in addition to the system control function normally required for a mobile phone terminal, the reception electric field intensity level detected by the detection means or the reception field strength level detected by the reception means. Based on the received electric field strength information received, control means for optimizing the transmission power to the required minimum, and the drain bias currents of the FETs J1 and J2 are linearly amplified in conjunction with the setting of the control means. Is provided with a control means for setting the drain current of the FET Jx so as to have a minimum required value for maintaining the above.

The control information from the control means is given to the variable setting circuit 15 of the RF power amplifier circuit 10 as an external control signal in the form of a digital signal.

The above-mentioned control means can be constructed by software using a general-purpose control means so-called MPU or CPU which is made into a microcircuit.

Next, the operation will be described.

As described above, the gate bias voltage (Vo) of the dummy FET Jx is variably controlled so that the drain current Ix flowing through the FET Jx has a predetermined magnitude. This dummy FET Jx is an FE that forms an RF amplification stage.
The FETs of the same type are formed to have the same channel length and a smaller channel width than TJ1 and J2.

Therefore, the gate bias voltage (Vo) applied to the dummy FET Jx is set to the above FETs J1 and J2.
Of the gate bias voltage (Vo), a drain current having a constant proportional relationship with the drain current Ix flowing through the dummy FET Jx flows as a bias current through the FETs J1 and J2. As a result, the gate bias voltage (Vo) of the FETs J1 and J2 is the same as that of the dummy FET Jx.
The drain bias currents flowing through ETJ1 and J2 are variably controlled to have a predetermined magnitude. The control value of the drain bias current is set by the variable setting circuit 15.

Thus, the RF power amplifier circuit 1 described above is used.
In 0, FETs J1 and J2 that constitute the amplification stages 11 and 12
When a gate bias voltage (Vo) is applied to the gate bias voltage, the target drain bias current is first set, and the gate bias voltage at which the set drain bias current flows is variably set in a self-aligned manner by the negative feedback control operation. To be done. Then, the drain bias current can be arbitrarily set by the variable setting circuit 15.

As a result, even if the characteristics of the FETs J1 and J2 forming the amplification stages 11 and 12 of the RF power amplifier circuit 10 vary depending on various conditions such as the manufacturing process or mounting, the FETs J1 and J2 are amplified to a predetermined level. The optimal bias voltage (Vo) for performing the operation can be set in a self-aligning manner with good reproducibility without adjustment.

Therefore, for example, it is effective in reducing the size and weight of a mobile communication terminal device using a radio signal in the microwave region of 1 GHz or more and operating for a long time on a battery, and individual adjustments that significantly reduce the suitability for production. It is possible to perform stable and efficient RF power amplification even under the use condition of a single power source, without the need for.

Further, when a CDMA mobile communication terminal device is constructed using the RF power amplifier circuit 10 described above, even if the transmission power is set to a large degree for optimization,
As a result, it is possible to automatically give a bias condition that is always optimized according to the set transmission power.

Further, by forming the FETs J1, J2 and Jx on the same semiconductor chip in a thermally coupled state,
The similar relationship between J1, J2 and Jx has become even closer,
This makes it possible to further improve the accuracy of bias setting.

FIG. 2 shows the RF power amplifier circuit 1 shown in FIG.
An operating characteristic of 0 is shown.

In FIGS. 9A and 9B, Id is FET
The drain current of J1 (J2), Vg is the FET J1
The gate bias voltage of (J2) is shown.

FIG. 9A shows the case where the drain bias current Io is set so that the maximum output is obtained. In this case, the drain bias current Io is set substantially at the center of the linear change region of the drain current. The gate bias voltage (Vo) is a predetermined drain bias current Io due to the negative feedback operation performed by the bias generation circuit 14 described above.
Is variably controlled to flow. FET J1 (J2)
Linearly amplifies the input signal while the drain bias current Io flows.

FIG. 7B shows the case where the drain bias current Io is set small. In this case, the drain bias current Io is set at a position much lower than the center of the linear change region of the drain current. As a result, the amplitude range of the drain current for performing the linear amplification is narrowed, but at the time of low output operation, it is possible to reduce the power consumption due to the small drain bias current Io. Also in this case, the gate bias voltage (Vo) is variably controlled by the negative feedback operation performed by the bias generation circuit 14 described above so that the drain bias current Io that is set small flows.

It should be noted here that, by first setting the drain bias current Io, the gate bias voltage (Vo) at which the set drain bias current Io flows is automatically set. That is, the drain bias current Io that normally appears as a result of the gate bias can be set suddenly here without being aware of the gate bias. This makes it possible to finely set the minimum necessary drain bias current Io for performing the linear amplification operation, and avoid waste of continuing to flow a bias current more than necessary.

FIG. 3 is a detailed circuit diagram of the RF power amplifier circuit 10 focusing on the vicinity of the bias generation circuit 14 of FIG.

In the figure, the variable voltage generating circuit 17 is
The oscillator circuit 171, the variable gain circuit (VCA) 172, and the charge pump circuit 173 are included. The charge pump circuit 173 is composed of capacitive elements C1 and C2 which are passive elements and diodes D1 and D2. Oscillation circuit 17
The oscillation output of 1 is given to the charge pump circuit 173 via the variable gain circuit 172.

In the charge pump circuit 173, the pulse current output from the oscillating circuit 171 through the variable gain circuit 172 is switched by the diodes D1 and D2 for each current direction to flow to C1 and C2, whereby the capacitive element C1 is obtained.
Is charged with a negative voltage. The negative voltage charged in C1 is output as the gate bias voltage (Vo),
It is distributed to each gate of FETs Jx, J1, and J2.

The magnitude of the negative voltage (Vo) charged in C2 changes depending on the transfer gain of the variable gain circuit 172. The transfer gain of the variable gain circuit 172 is the dummy FET J
It is variably controlled by the output of the comparison circuit 16 that compares the drain current Ix of 1 with a predetermined set value (Vr). As a result, the gate bias voltage (Vo) becomes
Negative feedback control is performed so that a predetermined drain current flows through x, J1, and J2. Variable gain circuit 172
Can use, for example, a variable resistance attenuation circuit using MOS transistors.

The resistor R4 is connected in parallel to the capacitive element C1 to form a discharge circuit for C1, thereby speeding the falling response of the gate bias voltage (Vo).

In this case, the oscillator circuit 171 which is an active circuit
The variable gain circuit 172 and the variable gain circuit 172 are both configured to operate with a positive power supply voltage (Vdd). As a result, the variable control of the negative voltage can be easily and smoothly performed by the positive voltage system and circuit.

The gate bias voltage (Vo) is negatively feedback controlled so that the drain current set by the variable setting circuit 15 flows. Therefore, when the transmission power optimization control is performed according to the electric field intensity of the received signal or the electric field intensity information of the local station transmitted radio wave fed back from the wireless communication partner station, the variable setting circuit 15 of the variable setting circuit 15 is linked with the control. If the set value is also controlled to be optimized, it is possible to always perform power amplification by a linear operation with minimum transmission power regardless of transmission power.

FIG. 4 shows FETs Jx and J used in the present invention.
Layout patterns of 1 and J2 are schematically shown.

In the figure, G indicates the gate electrode pattern of the FET, L indicates its channel length, and W indicates its channel width. As shown in FIG.
The dummy FET Jx of is the F of the RF power amplification stages 11 and 12.
ETJ1 and J2 are formed on the same semiconductor chip in a thermally coupled state, and have the same channel length L and a small channel width.

As described above, by forming the FETs J1, J2 and Jx on the same semiconductor chip in a thermally coupled state, the similar relationship between J1, J2 and Jx becomes more close to each other, whereby the bias setting accuracy is improved. Can be further increased.

FIG. 5 shows a configuration example of the variable voltage source 151 used in the variable setting circuit 15.

The variable voltage source 151 shown in the figure is composed of a voltage dividing circuit including a fixed resistor R5 and a variable resistor circuit R6. The variable resistance circuit R6 includes a plurality of resistance elements r1 to r1.
r4 is selectively connected in parallel via the switch circuits S1 to S4, respectively.
Each S4 is individually turned on / off by a digital control signal provided from the outside (logic control unit 60). As a result, the combined resistance of any combination of the plurality of resistance elements r1 to r4 can be electrically variably set.

FIG. 6 shows another configuration example of the bias generation circuit 14.

The bias generation circuit 14 shown in the figure includes a drain load resistor R3 for supplying a current to the drain of the dummy FET Jx and a shunt resistor for shunting a part of the current Ix supplied from the resistor R3 to the outside of the drain. In addition to having R9, this shunt resistance R9 is formed by using an electrically variably set resistance.

Drain voltage Vx of the dummy FET Jx
Is compared with a predetermined set voltage Vr in the comparison circuit 16,
The variable voltage control circuit 14 is controlled by this comparison output. As a result, negative feedback control is performed so that the drain voltage Vx of the dummy FET Jx becomes the predetermined set voltage Vr.

In this case, as the reference voltage Vr of the comparison circuit 16, a constant voltage obtained by dividing the power supply voltage (Vdd) by the resistors R7 and R8 is used. Jx drain current Vx
Is set by the magnitude of the current Ix2 flowing through the shunt resistor R9.

The shunt resistance R9 is composed of a plurality of resistance elements r1 to r.
4 are selectively connected in parallel via switch circuits S1 to S4, respectively. The dummy FET J is set by individually setting ON / OFF of each switch S1 to S4 of this variable resistance circuit by a digital control signal given from the outside (logic control unit 60).
The drain current Ix1 of x can be variably set.
In this way, the bias voltage (V that is negatively feedback controlled so that the predetermined drain current Ix1 flows through the dummy FET Jx).
o), the FETs J1 and J2 of the amplification stages 11 and 12 can be linearly operated with high accuracy under a predetermined drain bias current.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, the means for variably setting the drain bias current Io can also be realized by providing a switching means for variably setting the channel width of the dummy FET Jx. That is, by switching and varying the channel width of Jx, the drain current ratio between Jx and J1 and the drain current ratio between Jx and J2 can be arbitrarily variably set.

Further, the dummy FET used as the drain current detecting means can also be used as a small signal amplifying circuit as long as the DC operating point thereof is not affected.

In the above description, the case where the invention made by the present inventor is applied to the mobile phone terminal which is the field of application which is the background of the invention has been mainly described, but the invention is not limited thereto and, for example, a solar cell or the like. It is also applicable to a PHS base station whose power source is backed up in, a wireless beacon transmission device, or the like.

[0094]

EFFECT OF THE INVENTION Among the inventions disclosed in the present application,
The following is a brief description of the effect obtained by the typical one.

That is, individual adjustments that are effective for reducing the size and weight of a mobile communication terminal device that uses a radio signal in the microwave region of 1 GHz or higher and operating for a long time on a battery, and that significantly reduce the suitability for production. It is possible to obtain stable and efficient RF power amplification even under the use condition of a single power source without the need for the above.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an outline of a mobile communication terminal device to which the technology of the present invention is applied.

FIG. 2 is a diagram showing operating characteristics of an RF power amplifier circuit to which the technique of the present invention is applied.

FIG. 3 is a diagram showing a detailed circuit example of an RF power amplifier circuit according to the present invention.

FIG. 4 is a diagram schematically showing a layout pattern of an FET used in the present invention.

FIG. 5 is a diagram showing a configuration example of a variable voltage source for performing bias setting.

FIG. 6 is a diagram showing another configuration example of the bias generation circuit.

[Explanation of symbols]

10 RF power amplifier circuit J1, J2 1st FET 11 Final stage of multi-stage RF power amplifier circuit 12 Pre-stage of multi-stage RF power amplifier circuit 13 Output matching circuit 14 Bias generator Jx 2nd FET (dummy FET) 15 Variable setting circuit 151 Variable voltage source 16 Comparison circuit 17 Variable voltage generator 171 oscillator circuit 172 Variable gain circuit 173 Charge pump circuit 18 Negative feedback circuit Rx, R1-R9 resistance Cp, C1, C2 Capacitive element D1, D2 diode 20 RF reception preamplifier 31 duplexer (or antenna switch) 32 wireless transmitting / receiving antenna 41 Transmission side frequency conversion circuit (upverter) 42 Frequency converter on receiving side (downverter) 43 Frequency synthesizer 50 baseband unit 60 logic control unit 61 Operation panel 62 headset 70 Built-in battery

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-90707 (JP, A) JP-A-5-152978 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03F 1/00-3/72 H04B 1/04

Claims (5)

(57) [Claims] 1. The source is grounded by depletion operation.
And a first FET that performs RF power amplification,The It is the same type of FET as the first FET and has the same channel length.
Second FET with a narrow and narrow channel width
When,Increase the difference between the drain voltage of the second FET and the reference voltage.
A voltage comparison circuit that outputs the width Based on the output of the voltage comparison circuit , Positive power supply voltage to negative voltage
Has occurredthe aboveFirst FETandEach FET of the second FET
A variable voltage generation circuit that distributes a negative bias voltage to the gate,The gate of the first FET and the output of the variable voltage generating circuit
A first resistor connected in series with the force side, The gate of the second FET and the output of the variable voltage generation circuit
A second resistor connected in series with the force side, The output voltage of the variable voltage generating circuit is set to that of the second FET.
A bias voltage is applied to the gate through the second resistor in series.
The drain voltage is equal to the reference voltage.
Feedback control such as
The gate of the second FET is AC blocked from each other.
The above Drain of the second FET
The variable voltage is generated so that the
With a negative feedback circuit that controls the pathBe prepared, Output of the variable voltage generating circuit forming the negative feedback circuit
The voltage directly connects the first resistor to the gate of the first FET.
Configured to be applied as a bias voltage through the column
Has been An RF power amplifier circuit characterized by the above. Wherein said first FET is RF power amplifier circuit according to claim 1, characterized in that to form a linear amplifier. Wherein in the first FET and the second FET
Have but is formed by thermal bonding state on the same semiconductor chip
RF power amplifier circuit according to any of claims 1 4, characterized in that that. 4. The method of claim 1, characterized by comprising a variable setting circuit for setting in response to a signal from outside the drain current value of the <br/> second FET which is controlled by the negative feedback circuit 4. The RF power amplifier circuit according to any one of 3 to 3. 5. The source is grounded by depletion operation.
And a first FET that performs RF power amplification,The It is the same type of FET as the first FET and has the same channel length.
Second FET with a narrow and narrow channel width
When,Increase the difference between the drain voltage of the second FET and the reference voltage.
A voltage comparison circuit that outputs the width Based on the output of the voltage comparison circuit , Positive power supply voltage to negative voltage
Has occurredthe aboveFirst FETandEach FET of the second FET
A variable voltage generation circuit that distributes a negative bias voltage to the gate,The gate of the first FET and the output of the variable voltage generating circuit
A first resistor connected in series with the force side, The gate of the second FET and the output of the variable voltage generation circuit
A second resistor connected in series with the force side, The output voltage of the variable voltage generating circuit is set to that of the second FET.
A bias voltage is applied to the gate through the second resistor in series.
The drain voltage is equal to the reference voltage.
Feedback control such as
The gate of the second FET is AC blocked from each other.
The above Drain of the second FET
The variable voltage is generated so that the
With a negative feedback circuit that controls the path,Output of the variable voltage generating circuit forming the negative feedback circuit
The voltage directly connects the first resistor to the gate of the first FET.
Configured to be applied as a bias voltage through the column
Re , Control means for variably controlling the above set value according to the transmission output
HaveA mobile communication terminal device characterized by the above.