JP4012180B2 - Cmp用スラリー、研磨方法、および半導体装置の製造方法 - Google Patents
Cmp用スラリー、研磨方法、および半導体装置の製造方法 Download PDFInfo
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- JP4012180B2 JP4012180B2 JP2004231167A JP2004231167A JP4012180B2 JP 4012180 B2 JP4012180 B2 JP 4012180B2 JP 2004231167 A JP2004231167 A JP 2004231167A JP 2004231167 A JP2004231167 A JP 2004231167A JP 4012180 B2 JP4012180 B2 JP 4012180B2
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- surfactant
- polishing
- slurry
- insulating film
- cmp
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Organic Chemistry (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
Description
第1の界面活性剤のHLB値は3〜7が好ましく、この場合の曇点は19〜32℃程度である。また、第2の界面活性剤のHLB値は12〜18が好ましく、この場合の曇点は63〜80℃程度である。第1および第2の界面活性剤は、それぞれ単独でも、2種以上を組み合わせて用いてもよい。
図1乃至図3を参照して、本実施形態を説明する。
本発明の実施形態にかかるCMP用スラリーは、STI(Shallow trench isolation)の形成に適用することも可能である。図6および図7を参照して、本実施形態を説明する。
本発明の実施形態にかかるCMP用スラリーは、レジストCMPに適用することも可能である。図8乃至図10を参照して、本実施形態を説明する。
B:ポリオキシエチレンラウリルエーテル
C:アセチレングリコールポリエーテル付加物
D:ポリオキシエチレン・メチルポリシロキサン共重合体
表3に示されるように、No.24〜28のスラリーサンプルは、室温HLB値が3〜9の第1の界面活性剤と、室温HLB値が10〜20の第2の界面活性剤を含有しているので、エロージョンを20nm以下に抑えることができた。これらのスラリーサンプルにおいては、第1の界面活性剤の曇点はいずれも37+3℃以下であり、第2の界面活性剤の曇点はいずれも37℃より高い。界面活性剤の疎水部が、アセチレングリコールまたはシロキサンであるNo.25〜28のスラリーサンプルでは、エロージョンは18nm以下であり、特に、第1および第2の界面活性剤の疎水部がいずれもアセチレングリコールであるNo.25のスラリーサンプルでは、エロージョンは16nmとよりいっそう低減されている。このことから、レジスト膜に対しては、疎水部としてアセチレングリコールが効果的であることが確認された。
13…溝パターン; 14…バリアメタル膜; 15…配線材料膜
16…エロージョン; 17…導電性層; 20…ターンテーブル
21…研磨布; 22…半導体基板; 23…トップリング; 24…水供給ノズル
25…スラリー供給ノズル; 26…ドレッサー; 27…スラリー
31…CMPストッパー膜; 32…絶縁膜; 41…レジスト膜; 42…段差
43…露光用レジスト膜; 44…微細ホール; 45…ヴィアホール
46…バリアメタル膜; 47…配線材料膜; 48…導電性層; 49…プラグ
50…配線。
Claims (4)
- 研磨粒子と界面活性剤とを含有し、前記界面活性剤は、疎水部としてシロキサンまたはアセチレングリコールを有し室温でのHLB値が3〜7の第1のポリエーテル型非イオン界面活性剤と、疎水部としてシロキサンまたはアセチレングリコールを有し室温でのHLB値が12〜18の第2のポリエーテル型非イオン界面活性剤とを含むことを特徴とするCMP用スラリー。
- 前記第1のポリエーテル型非イオン界面活性剤は、曇点が19〜32℃であり、前記第2のポリエーテル型非イオン界面活性剤は、曇点が63〜80℃であることを特徴とする請求項1に記載のCMP用スラリー。
- ターンテーブル上に貼付された研磨布に、被研磨面を有する半導体基板を当接させる工程、および
前記研磨布上に、請求項1または2に記載のCMP用スラリーを滴下して、前記被研磨面を研磨する工程を具備することを特徴とする研磨方法。 - 半導体基板上に絶縁膜を形成する工程と、
前記絶縁膜に凹部を形成する工程と、
前記凹部の内部および前記絶縁膜の上に導電性材料を堆積して、導電性を有する層を形成する工程と、
前記絶縁膜の上に堆積された前記導電性材料を除去して前記絶縁膜を露出し、前記導電性材料を前記凹部内部に残置する工程とを具備し、
前記絶縁膜上に堆積された前記導電性材料の除去は、請求項1または2に記載のスラリーを用いたCMPにより行なわれることを特徴とする半導体装置の製造方法。
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