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JP2016219520A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP2016219520A
JP2016219520A JP2015100675A JP2015100675A JP2016219520A JP 2016219520 A JP2016219520 A JP 2016219520A JP 2015100675 A JP2015100675 A JP 2015100675A JP 2015100675 A JP2015100675 A JP 2015100675A JP 2016219520 A JP2016219520 A JP 2016219520A
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Japan
Prior art keywords
cutting
semiconductor device
qfn
plating layer
lead frame
Prior art date
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Pending
Application number
JP2015100675A
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English (en)
Japanese (ja)
Inventor
勝則 傳藤
Katsunori Dento
勝則 傳藤
昌一 片岡
Shoichi Kataoka
昌一 片岡
幹司 石橋
Kanji Ishibashi
幹司 石橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Towa Corp
Original Assignee
Towa Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Towa Corp filed Critical Towa Corp
Priority to JP2015100675A priority Critical patent/JP2016219520A/ja
Priority to TW105113231A priority patent/TWI645465B/zh
Priority to KR1020160056980A priority patent/KR101803183B1/ko
Priority to CN201610327073.0A priority patent/CN106169443A/zh
Publication of JP2016219520A publication Critical patent/JP2016219520A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2015100675A 2015-05-18 2015-05-18 半導体装置及びその製造方法 Pending JP2016219520A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2015100675A JP2016219520A (ja) 2015-05-18 2015-05-18 半導体装置及びその製造方法
TW105113231A TWI645465B (zh) 2015-05-18 2016-04-28 半導體裝置及其製造方法
KR1020160056980A KR101803183B1 (ko) 2015-05-18 2016-05-10 반도체 장치 및 그 제조 방법
CN201610327073.0A CN106169443A (zh) 2015-05-18 2016-05-17 半导体装置及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015100675A JP2016219520A (ja) 2015-05-18 2015-05-18 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
JP2016219520A true JP2016219520A (ja) 2016-12-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015100675A Pending JP2016219520A (ja) 2015-05-18 2015-05-18 半導体装置及びその製造方法

Country Status (4)

Country Link
JP (1) JP2016219520A (zh)
KR (1) KR101803183B1 (zh)
CN (1) CN106169443A (zh)
TW (1) TWI645465B (zh)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019057587A (ja) * 2017-09-20 2019-04-11 大口マテリアル株式会社 半導体素子搭載用基板及びその製造方法
JP2019102697A (ja) * 2017-12-05 2019-06-24 エイブリック株式会社 半導体装置およびその製造方法
CN110943064A (zh) * 2018-09-21 2020-03-31 新光电气工业株式会社 引线框架及其制造方法
JP2021057561A (ja) * 2019-09-26 2021-04-08 ローム株式会社 端子、半導体装置、およびこれらの製造方法
JP2022091907A (ja) * 2018-03-16 2022-06-21 ローム株式会社 半導体装置
JP2022531059A (ja) * 2019-03-08 2022-07-06 シリコニックス インコーポレイテッド 側壁メッキ層を有する半導体パッケージ
JP2022145046A (ja) * 2021-03-19 2022-10-03 株式会社東芝 半導体装置
JP7545957B2 (ja) 2019-12-24 2024-09-05 ヴィシャイ ジェネラル セミコンダクター，エルエルシー 導電性膜を備えた側壁メッキ用パッケージ方法
US12224232B2 (en) 2019-03-08 2025-02-11 Siliconix Incorporated Semiconductor package having side wall plating
JP7656508B2 (ja) 2021-07-14 2025-04-03 株式会社ディスコ 加工方法及び切削装置

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JP6800745B2 (ja) * 2016-12-28 2020-12-16 株式会社ディスコ 半導体パッケージの製造方法
CN108109972B (zh) * 2017-12-29 2020-03-06 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的半导体封装结构及其制造工艺
CN108206170B (zh) * 2017-12-29 2020-03-06 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的半导体封装结构及其制造工艺
CN108198804B (zh) * 2017-12-29 2020-03-06 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的堆叠封装结构及其制造工艺
CN108198790B (zh) * 2017-12-29 2020-03-06 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的堆叠封装结构及其制造工艺
CN108198797B (zh) * 2017-12-29 2020-03-06 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的半导体封装结构及其制造工艺
CN108198761B (zh) * 2017-12-29 2020-06-09 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的半导体封装结构及其制造工艺
CN109243988A (zh) * 2018-09-14 2019-01-18 上海凯虹科技电子有限公司 封装体及其封装方法
JP6827495B2 (ja) * 2019-05-16 2021-02-10 Ｔｏｗａ株式会社 半導体装置の製造方法
CN112713090B (zh) * 2019-10-24 2023-01-24 珠海格力电器股份有限公司 一种qfn器件的制备方法及qfn器件
CN111163595A (zh) * 2020-01-03 2020-05-15 珠海格力电器股份有限公司 一种芯片封装方法
CN113192852B (zh) * 2021-04-29 2023-12-15 长沙新雷半导体科技有限公司 一种芯片的封装方法
CN116246986A (zh) * 2023-05-10 2023-06-09 南京睿芯峰电子科技有限公司 具有外露引线框架的封装件及其制作方法
TWI865041B (zh) * 2023-09-14 2024-12-01 世界先進積體電路股份有限公司 封裝結構及其製造方法
CN117133746B (zh) * 2023-10-26 2024-01-30 成都电科星拓科技有限公司 用于双面焊接的方形扁平无引脚封装芯片结构及封装方法

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JPH11176856A (ja) * 1997-12-16 1999-07-02 Sanyo Electric Co Ltd 半導体装置の製造方法
JP2001185651A (ja) * 1999-12-27 2001-07-06 Matsushita Electronics Industry Corp 半導体装置およびその製造方法
JP2005038927A (ja) * 2003-07-16 2005-02-10 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP2008112961A (ja) * 2006-10-04 2008-05-15 Rohm Co Ltd 半導体装置の製造方法および半導体装置
JP2008186891A (ja) * 2007-01-29 2008-08-14 Denso Corp モールドパッケージおよびその製造方法ならびにモールドパッケージの実装構造
JP2013069814A (ja) * 2011-09-21 2013-04-18 Renesas Electronics Corp 半導体装置の製造方法
JP2013197426A (ja) * 2012-03-22 2013-09-30 Renesas Electronics Corp 半導体装置の製造方法および半導体装置

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US20090230524A1 (en) * 2008-03-14 2009-09-17 Pao-Huei Chang Chien Semiconductor chip package having ground and power regions and manufacturing methods thereof
KR20090113463A (ko) * 2008-04-28 2009-11-02 한미반도체 주식회사 반도체 제조장비의 인라인 쏘잉 시스템
JP5215980B2 (ja) * 2009-10-30 2013-06-19 株式会社三井ハイテック 半導体装置の製造方法
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JP2014007287A (ja) * 2012-06-25 2014-01-16 Renesas Electronics Corp 半導体装置の製造方法
KR101464605B1 (ko) * 2012-12-07 2014-11-24 시그네틱스 주식회사 솔더 접합 능력을 향상하는 큐. 에프. 엔 반도체 패키지 및 그의 제조방법
JP6218511B2 (ja) * 2013-09-02 2017-10-25 Ｔｏｗａ株式会社 切断装置及び切断方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11176856A (ja) * 1997-12-16 1999-07-02 Sanyo Electric Co Ltd 半導体装置の製造方法
JP2001185651A (ja) * 1999-12-27 2001-07-06 Matsushita Electronics Industry Corp 半導体装置およびその製造方法
JP2005038927A (ja) * 2003-07-16 2005-02-10 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP2008112961A (ja) * 2006-10-04 2008-05-15 Rohm Co Ltd 半導体装置の製造方法および半導体装置
JP2008186891A (ja) * 2007-01-29 2008-08-14 Denso Corp モールドパッケージおよびその製造方法ならびにモールドパッケージの実装構造
JP2013069814A (ja) * 2011-09-21 2013-04-18 Renesas Electronics Corp 半導体装置の製造方法
JP2013197426A (ja) * 2012-03-22 2013-09-30 Renesas Electronics Corp 半導体装置の製造方法および半導体装置

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019057587A (ja) * 2017-09-20 2019-04-11 大口マテリアル株式会社 半導体素子搭載用基板及びその製造方法
JP2019102697A (ja) * 2017-12-05 2019-06-24 エイブリック株式会社 半導体装置およびその製造方法
JP7033445B2 (ja) 2017-12-05 2022-03-10 エイブリック株式会社 半導体装置およびその製造方法
JP2022091907A (ja) * 2018-03-16 2022-06-21 ローム株式会社 半導体装置
JP7524244B2 (ja) 2018-03-16 2024-07-29 ローム株式会社 半導体装置
CN110943064A (zh) * 2018-09-21 2020-03-31 新光电气工业株式会社 引线框架及其制造方法
JP7473560B2 (ja) 2019-03-08 2024-04-23 シリコニックス インコーポレイテッド 側壁メッキ層を有する半導体パッケージ
US12224232B2 (en) 2019-03-08 2025-02-11 Siliconix Incorporated Semiconductor package having side wall plating
JP2022531059A (ja) * 2019-03-08 2022-07-06 シリコニックス インコーポレイテッド 側壁メッキ層を有する半導体パッケージ
US12211704B2 (en) 2019-03-08 2025-01-28 Siliconix Incorporated Semiconductor package having side wall plating
JP7326115B2 (ja) 2019-09-26 2023-08-15 ローム株式会社 端子、半導体装置、およびこれらの製造方法
JP2021057561A (ja) * 2019-09-26 2021-04-08 ローム株式会社 端子、半導体装置、およびこれらの製造方法
JP7545957B2 (ja) 2019-12-24 2024-09-05 ヴィシャイ ジェネラル セミコンダクター，エルエルシー 導電性膜を備えた側壁メッキ用パッケージ方法
JP7451455B2 (ja) 2021-03-19 2024-03-18 株式会社東芝 半導体装置
JP2022145046A (ja) * 2021-03-19 2022-10-03 株式会社東芝 半導体装置
JP7656508B2 (ja) 2021-07-14 2025-04-03 株式会社ディスコ 加工方法及び切削装置

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