JP2000294730A - System LSI chip and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect abnormality owing to an accidental cause such as a defect occurred in a system LSI chip and the mix of foreign matters by forming an interlayer insulating film on an element, layer having a memory cell, and forming wiring test structure for a whole second area on the interlayer insulating film. SOLUTION: In a via hole chain VC, via hole connection parts VH are installed on both ends of wiring IL3 and one end of wiring IL4 is connected to the via hole connection part VH at one end of wiring IL3. Wiring IL4 is arranged perpendicular to wiring IL3 and they are made into one group. The connection of the via hole connection part VH which is not connected to wiring IL4 in the other group to wiring IL4 in one group is repeated and they are made in a zigzag form. Several folding parts IL3a are installed midway and wiring test structure is formed for the whole area of a memory part in a second area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a system LSI chip having a test structure for wiring (Test Element Group: hereinafter referred to as TEG).

[0002]

2. Description of the Related Art In semiconductor devices such as LSIs, finer wirings and multi-layered semiconductor devices have been developed along with finer elements and higher integration. The wiring structure including the interlayer insulating film and the manufacturing process thereof have become complicated due to the miniaturization and multilayering of the wiring, and it is no exaggeration to say that the performance of the wiring affects the performance and the yield of the product now. In order to improve yield and process management, it is necessary to accurately and quickly evaluate the performance of wiring. Immediately after the process for checking whether there is no abnormality such as disconnection or short-circuit caused by accidental factors such as defects or foreign matter, and whether the wiring width etc. was formed as designed, etc. There are various methods such as evaluation and reliability evaluation by an accelerated test for checking the aging of completed chips (such as generation of voids in wiring due to migration).

[0003] In order to evaluate the performance of the wiring itself in a product chip, it is necessary to independently evaluate the performance without being affected by other circuit elements in the product chip. Is difficult and inefficient, so that various T
Evaluation has been performed using EG. Specifically, parameters such as the resistance value of such a wiring TEG are measured, and if different from the design values, observation with an emission microscope or O
Wiring is evaluated by detecting a portion having a defect or an abnormality using an optical method such as BIC (Optical Beam Induced Current) analysis.

[0004]

Conventional wiring TEGs include a method of manufacturing a test wafer in which only a wiring TEG is formed separately from a product wafer, and a method of forming a wiring TEG outside a product chip region of a product wafer. There was a case where an area was provided.

However, in the former case, since the test wafer is separate from the product wafer, there is a possibility that the test wafer does not accurately reflect an abnormality generated in the product wafer due to an accidental factor. In order to improve the detection rate of abnormalities caused by accidental factors, it is necessary to increase the frequency of producing test wafers since statistical investigation is required. However, this leads to an increase in product cost.

On the other hand, in the latter case, the provision of the wiring TEG region in the product wafer reduces the area occupied by the product chips and lowers the yield of the product chips, which leads to an increase in the cost of the product. In this case, it is possible to avoid the cost increase by reducing the wiring TEG region,
If the area of the wiring TEG region is reduced, the detection rate of abnormalities caused by accidental factors is reduced, so that sufficient inspection of the product cannot be expected.

As described above, in the conventional wiring TEG,
In order to improve the detection rate of abnormalities that occur in product chips due to accidental factors, an increase in cost was inevitable.

Therefore, it is conceivable to form the wiring TEG inside the product chip itself. There are some empty spaces inside the product chip, and these empty spaces are used as wiring TEG formation regions. As such an example, there is a technique described in JP-A-5-144917. Chip CP shown in FIG.
FIG. 2 is a plan view illustrating this technique. Chip C
P2 has an empty space 3 where the substrate wiring TEG is formed.
01 and the region 30 where the internal cell and the regular wiring are formed
2 and a region 303 where the I / O cell is formed.

If this technique is used, the wiring T is formed in the product chip.
Since the EG is formed, it is possible to detect an abnormality that has occurred in a product chip due to an accidental factor without manufacturing a large number of test wafers. Further, since the free space in the product chip is used, the yield of the product chip does not decrease. Therefore, it is possible to evaluate the quality of the wiring while avoiding the problem of the conventional wiring TEG.

However, in the technique disclosed in Japanese Patent Application Laid-Open No. 5-144917, there is only a description that the wiring TEG is formed in an empty space (for example, at the four corners of the chip). The difference in effect due to the above is not taken into account. That is, the chip C shown in FIG.
In the case of P2, the wiring TEG is formed in a separate area from the internal cell and regular wiring forming area 302 and the I / O cell forming area 303 in a plan view. , A product area) in a plan view, there is a possibility that an empty space is very small and the wiring TEG area cannot have a sufficient area.

Now, a chip having a multilayer wiring structure includes:
In some cases, there is a wide open space in addition to the plane where the product area exists. In a system LSI chip in which memory and logic are integrated, a multilayer wiring structure in which wiring exists in many layers in the logic portion is required,
In the memory section, generally, it is sufficient that about two upper wiring layers necessary for power / ground wiring and the like exist. Therefore, a considerably large empty space corresponding to the area of the memory unit exists on the upper wiring layer of the memory unit.

However, in the case of a system LSI, a metal film called a dummy pattern having a size of about several μm is usually laid in this empty space. This dummy pattern
Chemical mechanical polishing (hereinafter referred to as C) for forming a wiring film of a multilayer wiring structure in a logic portion.
MP)) to prevent dishing (dish-like depressions) from occurring on the surface of the interlayer insulating film in the memory portion during processing, and to reduce the area of the metal film in the memory portion and reduce the wiring film in the logic portion. In order to prevent a difference in etching rate between the logic portion and the memory portion during pattern formation, the metal portion is provided for the purpose of ensuring the balance of the density of the metal film.

FIGS. 10 and 12 show such a system LSI.
This is an example of the structure of the chip CP1. FIG.
0 shows a layout view in plan view of the memory unit MM and the logic unit LG on the chip, and FIG.
FIG. 9 is a plan view showing an arrangement of dummy patterns DP formed in an empty space on a memory cell array by enlarging a region RG in FIG. In FIG. 10, the memory unit MM
Are designed on the same scale as the logic part LG. In the system LSI chip, the ratio of the area occupied by the memory section MM varies, but usually, the memory section MM often occupies a somewhat large scale in the entire area of the system LSI chip CP1.

FIG. 12 is a sectional view taken along the line CC of FIG.
FIG. As shown in FIG.
Comprises an element layer 402 having a large number of memory cells MC (for example, a set of a DRAM and a capacitor) on a substrate 401,
Above it, a wiring layer 403 having power supply / ground wirings IL1 and IL2 and a dummy pattern layer 404 on which a large number of dummy patterns DP are formed are provided. The dummy pattern DP has a surface on the same plane as the surface of the wiring (not shown) of each layer in the multilayer wiring structure of the logic part LG. In FIG. 12, the dummy pattern layer 404 is used as an example.
Shows the case where three layers are formed. Note that, between the memory cell MC and the power / ground wiring IL1, between the power / ground wiring IL1 and the power / ground wiring IL2, between the power / ground wiring IL2 and the dummy pattern layer 404, and in the dummy pattern layer 404. An interlayer insulating film I is provided between each layer.
S0, IS1, IS2, IS3, IS4 are formed,
Each layer is insulated from each other. Then, a passivation film PV for protecting the surface is formed on the uppermost dummy pattern DP. In FIG. 12, the element layer 40
The layer on which the wiring IL1 immediately above the wiring 2 is formed is the first layer, and the wiring I
The layer on which L2 is formed is the second layer, the dummy pattern layer 404
Each layer in the order from the bottom as the third layer, the fourth layer, the fifth layer,
Each is displayed.

As described above, the memory unit MM of the chip CP1
In the third to fifth layers, although there is room for forming a wiring region having the same size as the area of the memory unit MM, the wiring region is not effectively used except for using as a dummy pattern.

According to the present invention, a dummy pattern layer which has not been effectively used among empty spaces in memory cells of a memory portion of a system LSI chip is used as a large-scale wiring TEG region while retaining a dummy pattern function. The purpose is to:

[0017]

Means for Solving the Problems Claim 1 of the present invention
A substrate having first and second regions on a surface thereof, a multilayer wiring structure formed on the first region of the substrate, and a multilayer wiring structure formed on the second region of the substrate; A system LSI chip comprising: an element layer having a memory cell; an interlayer insulating film formed on the element layer; and a wiring test structure formed over the entire area of the second region on the interlayer insulating film. is there.

According to a second aspect of the present invention,
2. The system LSI chip according to claim 1, wherein said multilayer wiring structure and said wiring test structure are formed in a common process.

According to a third aspect of the present invention,
3. The system LSI chip according to claim 2, wherein a fixed potential is applied to a part of said wiring test structure.

According to a fourth aspect of the present invention,
3. The system LSI chip according to claim 2, further comprising an electrode pad connected to said wiring test structure and having a surface flush with a portion of said wiring test structure farthest from said substrate.

According to a fifth aspect of the present invention, there is provided:
First, preparing a substrate having first and second regions on a surface
A second step of forming an element layer having a memory cell on the second region, and a third step of forming a first interlayer insulating film on the first region and on the element layer Process and
Forming a first conductive film on the first interlayer insulating film;
Patterning the first conductive film to form a multilayer wiring structure on the first interlayer insulating film in the first region, and forming the first interlayer insulating film in the second region. Forming a wiring test structure over the entire area of the second region on the film, wherein the wiring test structure and the multilayer wiring structure are also formed to extend in the thickness direction of the substrate. In the case, a sixth step of further forming a second interlayer insulating film so as to cover the wiring test structure and the multilayer wiring structure, and patterning the second interlayer insulating film,
A seventh step of forming a via hole exposing the wiring test structure and the multilayer wiring structure, and an eighth step of forming a second conductive film on the second interlayer insulating film following the seventh step. Patterning the second conductive film so as to extend and form the multilayer wiring structure on the second interlayer insulating film in the first region; A ninth step of forming the wiring test structure so as to extend on the second interlayer insulating film.
Is a step of forming a portion of the wiring test structure farthest from the substrate, the method further comprises forming an electrode pad connected to the wiring test structure on the first or second interlayer insulating film. This is a method for manufacturing a system LSI chip to be formed.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 In this embodiment,
A system L provided with a continuous wiring structure having a large number of via-hole connecting portions (hereinafter, referred to as a via-hole chain) as a wiring TEG in a dummy pattern layer of a memory portion.
It is an SI chip.

FIG. 1 is an enlarged view of a region RG when a via hole chain VC is formed as a wiring TEG in a dummy pattern layer above the memory section MM of the system LSI chip CP1 shown in FIG. 2 shows an example of the array.

The via hole chain VC is formed by a lower wiring IL3 via an upper wiring IL4 and an interlayer insulating film IS3.
And a plurality of via-hole connecting portions VH connecting them are formed and connected to each other. For example, in the case of FIG. 1, the via hole chain VC includes a wiring IL3, a via hole connecting part VH provided at both ends of the wiring IL3, and a via hole connecting part VH at one end of the wiring IL3.
And a wiring IL4 disposed at a right angle to the wiring IL3 and having one end connected to the wiring IL3. One set of the wiring IL4 is connected to the via hole connecting portion VH that is not connected to the wiring IL4 in the other set. The connection is repeated to form a zigzag shape. Further, some folded portions IL3a are provided on the way, and are formed over the entire area of the memory unit MM. Further, electrode pads a and b are connected to both ends of the via hole chain VC. A similar example of such a via hole chain is disclosed in, for example, Japanese Patent Application Laid-Open No. 4-290.
Although it is described in Japanese Patent Application Laid-Open No. 242, there is no example provided in an empty space on a memory cell of a memory unit as in this embodiment.

FIG. 2 is a view showing a cross section taken along the line AA in FIG. The memory section MM in which the via hole chain VC is formed has a memory cell M
C (for example, a set of a DRAM and a capacitor), a wiring layer 103 having, for example, power / ground wirings IL1 and IL2, and a wiring IL thereon.
3, a TEG / dummy pattern layer 104a having a via hole chain VC composed of IL4 and a via hole connection portion VH, and a dummy pattern layer 104b having a dummy pattern DP. Also, the memory cell MC
Between the power supply / ground wiring IL1 and the power supply / ground wiring IL1
Between power supply / ground wiring IL2 and power supply / ground wiring IL2
Between the wiring IL3 and the wiring IL3, between the wiring IL3 and the wiring IL4,
And interlayer insulating films IS0, IS1, IS2, IS3, IS4 between the wiring IL4 and the dummy pattern DP, respectively.
Is formed, and the respective layers are insulated from each other. And
A passivation film PV for protecting the surface is formed on the uppermost dummy pattern DP. In FIG. 2, the layer on which the power / ground wiring IL1 is formed is the first layer, the layer on which the power / ground wiring IL2 is formed is the second layer, and the wiring IL is formed.
The layer where 3 is formed is shown as a third layer, the layer where the wiring IL4 is formed is shown as a fourth layer, and the layer where the dummy pattern DP is formed is shown as a fifth layer. Further, electrode pads a and b are connected to both ends of the via hole chain VC. The electrode pads a and b are, for example, the uppermost layer of the system LSI chip (the fifth layer in the case of FIG. 2) separately from the electrode pads in the product area.
(Not shown).

Although not shown, when forming the power supply / ground wirings IL1 and IL2, the wirings IL3 and IL4, the dummy pattern DP and the interlayer insulating films IS0 to IS4, the wiring and the interlayer are also formed in the logic part LG in a common step. An insulating film is formed.

When the system LSI chip according to the present embodiment is used, since the TEG of the via hole chain VC is formed in the dummy pattern layer in the multilayer wiring structure of the memory section MM, defects and foreign matter mixed in the product chip are generated. And the like can be detected, and the performance of the wiring itself can be evaluated independently of other circuit elements in the product chip. That is, parameters such as the resistance value of the via hole chain VC are measured to determine whether or not the values deviate from the design values. If the values deviate beyond the allowable range, a defect or abnormality is detected using an emission microscope or the like. To analyze the performance of the wiring of the product chip. Further, since the memory portion occupies a certain large area in the system LSI chip, a large-scale wiring TEG extending over the entire memory portion MM can be formed on the memory cell. The abnormality detection rate is higher than when the wiring TEG is formed. Further, since the via hole chain VC is formed in the same step as the wiring in the upper layer of the logic part LG, the wirings IL3 and IL4 are similarly subjected to the CMP processing when the wiring in the upper layer of the logic part LG is subjected to the CMP processing. Dishing hardly occurs on the surface of the interlayer insulating film in the part,
In addition, the balance of the density of the metal film can be ensured when forming the wiring metal pattern. That is, it has a function not only as the wiring TEG but also as a dummy pattern. After the performance evaluation, the wiring TE of the via hole chain VC
Since G is a metal film that is not energized, it also functions as an electrical shield that prevents electrical effects from the chip surface on the memory unit.

Embodiment 2 This embodiment is not a wiring TEG extending over two layers as in the via hole chain in the first embodiment, but a wiring TE for short-circuit detection of one layer.
System LS with G in dummy pattern layer of memory section
This is an I chip.

FIG. 3 is an enlarged view of a region RG of the memory portion MM of the system LSI chip CP1 shown in FIG. 10 when the TEG of the short-circuit detection wiring patterns SH1 and SH2 is applied to the dummy pattern layer. It is. Each of the short-circuit detecting wiring patterns SH1 and SH2 is a comb-shaped wiring pattern, and is arranged such that one comb tooth is positioned in a gap between the other comb teeth so as not to contact each other. It is formed over the entire area of the MM. The electrode pads a and b are provided at the ends of the short-circuit detection wiring patterns SH1 and SH2, respectively. A similar example of such a short-circuit detection wiring pattern is described in, for example, Japanese Patent Application Laid-Open No. 5-144917, but is provided in an empty space on a memory cell of a memory unit as in the present embodiment. There are no examples.

The patterns SH1 and SH2 are formed on one of the dummy pattern layers 404 in FIG. 12 in place of the dummy pattern DP, and the electrode pads a and b are formed.
However, for example, the system L is provided separately from the electrode pads in the product area.
Embodiment 1 if formed on the uppermost wiring layer of the SI chip
Similarly to the above, a large-scale wiring TEG is built in the system LSI chip.

When the system LSI chip according to the present embodiment is used, the short-circuit detection wiring patterns SH1 and SH1 are utilized by using the dummy pattern layer in the multilayer wiring structure of the memory unit MM.
Since the SH2 wiring TEG is formed, it is possible to detect an abnormality due to an accidental factor such as a defect generated in a product chip or a foreign substance. That is, the short-circuit detection wiring patterns SH1,
By measuring the resistance value between the electrode pads a and b of the SH2, it is possible to determine whether a short circuit has occurred between the wirings. If foreign matter or the like is mixed, the foreign matter or the like short-circuits the short-circuit detection wiring patterns SH1 and SH2,
This is because the resistance value between the electrode pads a and b is reduced. Furthermore, as in the case of the system LSI chip according to the first embodiment, since a large-scale wiring TEG over the entire area of the memory unit MM can be formed on the memory cell, the wiring TEG can be formed in a slight empty space on the same plane as the product area. Abnormality detection rate is higher than when forming. It also functions as a dummy pattern and an electric shield.

Embodiment 3 FIG. The present embodiment is a system LSI chip provided with a disconnection detection line TEG of one layer in a dummy pattern layer of a memory portion.

FIG. 4 is an enlarged view of a region RG in the case where the TEG of the disconnection detection wiring pattern WB is applied to the dummy pattern layer in the memory portion MM of the system LSI chip CP1 shown in FIG. . The disconnection detection wiring pattern WB is a pattern in which one wiring is repeatedly folded in a U-shape, and is formed over the entire area of the memory unit MM. Electrode pads a and b are connected to both ends. Note that a similar example of such a disconnection detection wiring pattern is described in, for example, Japanese Patent Application Laid-Open No. 10-189679, but is provided in an empty space on a memory cell of a memory unit as in this embodiment. There are no examples.

The pattern WB is formed on one of the dummy pattern layers 404 in FIG. 12 in place of the dummy pattern DP, and the electrode pads a and b are, for example, separately from the electrode pads in the product area. If it is formed on the uppermost wiring layer of the chip, a large-scale wiring TEG is built in the system LSI chip, as in the first or second embodiment.

When the system LSI chip according to the present embodiment is used, the wiring TEG of the disconnection detection wiring pattern WB is formed by using the dummy pattern layer in the multilayer wiring structure of the memory unit MM. An abnormality caused by an accidental factor such as a defect generated by the above or a foreign substance can be detected.
That is, by measuring the resistance value of the disconnection detection wiring pattern WB, it is possible to determine whether or not a disconnection has occurred between the wirings. If there are defects,
This is because the defect or the like causes disconnection in the disconnection detection wiring pattern WB, and increases the resistance value between the electrode pads a and b. Further, the system L according to the first or second embodiment
As in the case of the SI chip, a large-scale wiring TEG can be formed over the entire area of the memory section MM on the memory cell, so that the abnormality detection rate is lower than when the wiring TEG is formed in a slightly empty space on the same plane as the product area. Is high. It also functions as a dummy pattern and an electric shield.

Embodiment 4 FIG. In this embodiment, the wiring TE
This is a system LSI chip in which one electrode pad of G is omitted and a power supply potential or a ground potential in a product area is applied instead.

FIG. 5 shows a system L according to the third embodiment.
FIG. 9 is a diagram illustrating a case where, for example, an SI chip is connected to a power / ground wiring IL2 via a via-hole connection portion VHa instead of providing an electrode pad a at one end of a TEG of a disconnection detection wiring pattern WB, for example. Also, FIG.
FIG. 6 illustrates a cross section taken along a cutting line BB in FIG. 5. The memory unit MM on which the disconnection detection wiring pattern WB is formed.
Comprises an element layer 202 having a large number of memory cells MC on a substrate 201, and a wiring layer 20 having power / ground wirings IL1 and IL2 thereon, as in the first embodiment.
3, a TEG / dummy pattern layer 204a having a disconnection detection wiring pattern WB, and a dummy pattern layer 204b having a dummy pattern DP. In addition, interlayer insulating films IS0, IS1, IS2, IS3,
IS4 is formed and each layer is insulated from each other. Then, a passivation film PV for protecting the surface is formed on the uppermost dummy pattern DP. Also,
One end of the disconnection detection wiring pattern WB is connected to the electrode pad b, and the other end is connected to the via hole connection portion VHa via the power supply / ground wiring IL2 as described above.

When the system LSI chip according to the present embodiment is used, one electrode pad can be omitted for one wiring TEG pattern, so that the number of electrode pads requiring a large area can be reduced, and a product area can be reduced. The electrode pad can be widened. Further, since the power supply potential or the ground potential of the product region is applied to the wiring TEG, the wiring TEG after the performance evaluation is a metal film having a fixed potential, and a more effective electric shielding function can be obtained.

Note that even if one end of the wiring TEG is connected to the power supply potential or the ground potential in the product area, the power supply / ground wiring is
Since only the capacitive load of EG is added, the wiring TEG
Has no adverse effect on the product area.

Embodiment 5 In this embodiment, the wiring TE
This is a system LSI chip provided with electrode pads at both ends of a wiring TEG in a layer where G exists.

FIG. 7 shows a system L according to the first embodiment.
Taking the SI chip as an example, the electrode pads a and b at both ends of the wiring TEG of the via hole chain VC are connected to the uppermost wiring layer 5.
It is a figure which shows about the case where it is provided also in the 4th layer in addition to the 4th layer. The left half of the figure shows the same portion as the third to fifth layers of the structure of the memory unit MM shown in FIG. However, instead of the wiring IL3, the wiring PL connected to the electrode pad a is connected to the via hole connection portion VHd located at the final end of the wiring TEG of the via hole chain VC. The right half of the figure shows the structure of the electrode pad a. Wiring PL
Is connected to an electrode pad P4 formed in the fourth layer via a via hole connection portion VHb. Further, the electrode pad P4 is connected to an electrode pad P5 formed in the fifth layer via a via hole connection portion VHc.

Such a system LSI chip is formed as follows. Note that the configuration of a portion located closer to the substrate 101 than the interlayer insulating film IS3 is described in FIG.
2 is the same as that shown in FIG. First, the memory cell MM on the substrate 101 is
C and an interlayer insulating film IS0 are formed to form an element layer 102. At this time, a logic element and the like are formed in the logic part LG as in the memory part MM. And the memory unit M
M is a power / ground wiring IL1, an interlayer insulating film IS1, a power /
The ground wiring IL2 and the interlayer insulating film IS2 are formed in this order. After that, a metal film is formed on the surface of the interlayer insulating film IS2, and is patterned to form the wirings IL3 and PL. Then, an interlayer insulating film IS3 is formed so as to cover the wirings IL3 and PL.
To form Then, a via hole connected to the wiring IL3 is formed in the interlayer insulating film IS3 by using a photolithography technique, a metal film is formed on the surface of the interlayer insulating film IS3, and the via hole is filled with the metal film to form a via hole connecting portion VH,
VHb and VHd are formed. Then, the metal film is patterned to form the wiring IL4 and the electrode pad P4. FIG. 8 is a cross-sectional view showing the structure obtained in the steps up to here. The power supply / ground wirings IL1 and IL2 and the wiring IL
3, when forming the IL4 and the interlayer insulating films IS0 to IS3, the wiring and the interlayer insulating film are formed in the logic part LG in a common step, and the multilayer wiring structure is formed at the same time.

Normally, the electrode pads of the wiring TEG are so arranged that the probe can be contacted at the time of testing after completion of the chip.
It is sufficient to provide only the uppermost wiring layer in the multilayer wiring structure. However, immediately after the formation of the wiring TEG, the wiring TEG
If the performance evaluation can be performed, an abnormality in the wiring can be found at an early stage of the process. Therefore, as shown in FIG. 8, if the formation of the electrode pad P4 is completed when the fourth-layer wiring IL4 is formed on the surface of the interlayer insulating film IS3 and the via hole chain VC is completed, the subsequent processes are performed. The quality of the wiring can be evaluated at an early stage without passing through, and defective chips can be selected. By doing so, it is possible to prevent the subsequent process from being performed on the defective chip having an abnormality in the wiring, so that no waste occurs. In the case of the via hole chain VC, since the wiring TEG extends over the upper and lower two layers, the electrode pad P4 is formed in the same fourth layer as the layer on which the wiring IL4, which is the upper layer wiring, is formed. In the case of a wiring TEG extending over, an electrode pad may be formed on the uppermost layer of the wiring TEG.

When a defect or an abnormal portion is detected by an optical method after the completion of the chip, the wiring TE is determined to be present if the upper wiring (the dummy pattern DP in FIG. 7) is present.
Since G is shielded, it is difficult to detect a defective or abnormal location. However, if the electrode pad P4 is also formed at the time when the via hole chain VC is completed as described above, it is necessary to detect a defect or abnormality using an optical method without an upper wiring serving as a shield. Can be easily detected.

Then, for the chip in which no abnormality was recognized in the stage of FIG. 8, an interlayer insulating film IS4, a via hole connection portion VHc, an electrode pad P5, a dummy pattern DP, and a passivation film PV were formed. As shown in (1), a system LSI chip may be completed so that an acceleration test or the like after completion can be performed.

When the system LSI chip according to the present embodiment is used, since the electrode pads of the wiring TEG are also formed on the same layer as the layer on which the wiring TEG is formed, the wiring TE
Immediately after the formation of G, the performance of the wiring TEG can be evaluated.
Therefore, an abnormality can be found at an early stage of the process. In addition, it is possible to detect a defect or an abnormal portion by using an optical method without an upper wiring layer serving as a shield for the wiring TEG, so that the abnormality can be easily detected.

Others. In each of the above embodiments,
Although the case has been described where the wiring TEG in the dummy pattern layer of the memory unit MM is one type, a plurality of types of wiring TEG may be formed in one system LSI chip.

[0048]

According to the system LSI chip of the present invention, since the wiring test structure is formed on the interlayer insulating film in the second region, the system LSI chip can be used.
Anomalies due to accidental factors such as defects occurring in the chip and inclusion of foreign matter can be detected, and the performance of the wiring test structure can be evaluated independently of other elements in the system LSI chip. Further, since a large-scale wiring test structure can be formed over the entire second region on the element layer via an interlayer insulating film, the wiring test structure is formed in a slight empty space in the same plane as the second region. System L
The detection rate of an abnormality caused by an accidental factor such as a defect generated in the SI chip or a foreign substance is high. After completion of the wiring performance evaluation, the wiring test structure also functions as an electric shield for the second region.

According to the system LSI chip of the present invention, since the wiring test structure is formed in the same step as the multilayer wiring structure, the multilayer wiring structure in the first region is subjected to the CMP processing. At the time of formation, the wiring test structure in the second region is also subjected to the CMP treatment, so that dishing hardly occurs on the surface of the interlayer insulating film in the second region.
In addition, the balance of the density of the wiring film can be secured between the first region and the second region. That is, the wiring test structure also has a function as a dummy pattern.

If the system LSI chip according to claim 3 of the present invention is used, one electrode pad can be omitted for one wiring TEG pattern, so that the number of electrode pads requiring a large area can be reduced, and the product area can be reduced. The electrode pad can be widely used. In addition, since a fixed potential is applied, the wiring test structure after the performance evaluation is a conductive film having a fixed potential, and a more effective electrical shielding function can be obtained.

When the system LSI chip according to claim 4 of the present invention is used, a defect or an abnormal part is detected by an optical method without an upper wiring layer serving as a shield for the wiring test structure. This makes it easy to detect abnormalities.

According to the method of manufacturing a system LSI chip of the present invention, when forming a portion of the wiring test structure farthest from the substrate, the electrode pads connected to the wiring test structure are also formed. Since the wiring test structure is formed, the quality of the wiring test structure can be evaluated immediately after the formation of the wiring test structure, and it is possible to detect an abnormality at an early stage of the process and select a defective chip. By doing so, it is possible to prevent the subsequent process from being performed on the defective chip having an abnormality in the wiring, so that no waste occurs. In addition, a defect or abnormality can be detected using an optical method without an upper wiring layer serving as a shield for the wiring test structure, so that the abnormality can be easily detected.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a part of a system LSI chip according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a cross section of the system LSI chip according to the first embodiment of the present invention;

FIG. 3 is a diagram illustrating a part of a system LSI chip according to a second embodiment of the present invention;

FIG. 4 is a diagram showing a part of a system LSI chip according to a third embodiment of the present invention;

FIG. 5 is a diagram illustrating a part of a system LSI chip according to a fourth embodiment of the present invention;

FIG. 6 is a diagram illustrating a cross section of a system LSI chip according to a fourth embodiment of the present invention;

FIG. 7 is a diagram showing a cross section of a system LSI chip according to a fifth embodiment of the present invention.

FIG. 8 is a diagram showing a cross section of a system LSI chip before reaching FIG. 7;

FIG. 9 is a diagram showing a conventional semiconductor device.

FIG. 10 is a diagram showing a system LSI chip.

FIG. 11 is a diagram showing a part of a conventional system LSI chip.

FIG. 12 is a diagram showing a cross section of a conventional system LSI chip.

[Explanation of symbols]

101 substrate, 102 element layer, 104a dummy pattern layer, IS interlayer insulating film, VC via hole contact, SH1, SH2 short-circuit detection wiring pattern, WB
Disconnection detection wiring pattern, P4, P5 electrode pads.

Claims (5)

[Claims] A substrate having first and second regions on a surface thereof; a multilayer wiring structure formed on the first region of the substrate; and a multilayer wiring structure formed on the second region of the substrate; A system LSI chip comprising: an element layer having a memory cell; an interlayer insulating film formed on the element layer; and a wiring test structure formed over the entire area of the second region on the interlayer insulating film. 2. The system LSI chip according to claim 1, wherein said multilayer wiring structure and said wiring test structure are formed in a common process. 3. The system LSI chip according to claim 2, wherein a fixed potential is applied to a part of said wiring test structure. 4. The system LSI chip according to claim 2, further comprising an electrode pad connected to said wiring test structure and having a surface flush with a portion of said wiring test structure farthest from said substrate. 5. A first step of preparing a substrate having first and second regions on a surface, a second step of forming an element layer having a memory cell on the second region, A third step of forming a first interlayer insulating film on the first region and on the element layer; and a fourth step of forming a first conductive film on the first interlayer insulating film.
Patterning the first conductive film to form a multilayer wiring structure on the first interlayer insulating film in the first region;
The second region is formed on the first interlayer insulating film in the second region.
A fifth step of forming a wiring test structure over the entire area of the region, wherein the wiring test structure and the multilayer wiring structure are formed so as to extend also in the thickness direction of the substrate. A sixth step of further forming a second interlayer insulating film so as to cover the structure and the multilayer wiring structure; and patterning the second interlayer insulating film to expose the wiring test structure and the multilayer wiring structure. A seventh step of forming a via hole to be formed, and a second step on the second interlayer insulating film following the seventh step.
An eighth step of forming a conductive film, and patterning the second conductive film to extend and form the multilayer wiring structure on the second interlayer insulating film in the first region. A ninth step of extending and forming the wiring test structure on the second interlayer insulating film in the second region, wherein the fifth or ninth step includes the step of forming the wiring test structure. Forming a part farthest from the substrate, the method further comprises forming an electrode pad connected to the wiring test structure on the first or second interlayer insulating film. Method.