JP2003332449A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a manufacturing method in which a defective wiring layer is found in a subsequent process, removed to the wiring layer, and the layer is reconstructed to reduce a feedback time. SOLUTION: In manufacturing a semiconductor device having a multilayer wiring layer on an element formed on a semiconductor substrate, a step of forming a test element for inspecting a defect of the wiring layer (S100).
And a step of forming one or several wiring layers connected to the test element (S101), and a step of inspecting the wiring layer using the pads and the test element after forming the wiring layer (S102, S103) And) removing the defective wiring layer if the wiring layer is defective (S104).
Forming the removed wiring layer again. By removing and rebuilding the wiring layer immediately after the defective wiring layer, the manufacturing yield can be improved and the feedback time can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device in which a decrease in yield of the semiconductor device due to a wiring failure in a multilayer wiring structure formed on an element is prevented. is there.

[0002]

2. Description of the Related Art In the process of manufacturing a semiconductor device, after a required element is formed by performing an element isolation step, an impurity diffusion step, etc. on a semiconductor substrate, an interlayer insulating film and a via such as a contact hole and a through hole are formed on the upper layer thereof. A wiring process for forming a wiring for electrically connecting to the element is performed.
In recent years, as semiconductor devices have been highly integrated,
A semiconductor device having more than ten wiring layers (hereinafter referred to as a super-multilayer wiring semiconductor device) is provided, and in such a super-multilayer wiring semiconductor device, a large number of wiring steps are used in manufacturing the semiconductor device. Therefore, it is one of the important factors to reduce the defect rate in each wiring layer and the via for connecting the wiring layer to the underlying element or wiring layer.

For this purpose, normally, after the semiconductor device and the wiring layer above it are all manufactured to complete the manufacture of the semiconductor device, the semiconductor device or a test element formed in a part of the semiconductor device is tested. The inspection process is executed to measure the defect rate and investigate the cause of the defect.
Based on the results, a method is adopted in which measures are taken during the process to reduce defects. However, with this method, in an ultra-multilayered wiring semiconductor device, there are so many steps that cause a defect in the wiring layer, and it is very difficult to determine the cause of the defect. In addition, since there are many wiring steps in a super multi-layer wiring semiconductor device, the number of manufacturing days of the semiconductor device becomes very long. Therefore, when a defect analysis of the semiconductor device is performed after the semiconductor device is completed, the cause of the defect can be determined and , Feedback to measure and confirm effect is delayed. Therefore, from the viewpoint of improving the yield of products at an early stage, feedback by measurement after manufacturing takes a long time to confirm the effect, and is not sufficient.

Further, it has been attempted to identify a cause of a defect in a wiring layer of a manufactured semiconductor device and remove the upper wiring layer up to that layer to rebuild the wiring layer. However, the wiring layer causing the defect is a lower layer. It is difficult to remove the upper wiring layer from the entire surface of the wafer with accuracy. In this regard, for example, Japanese Patent No. 3139433 discloses a manufacturing method in which when a defect occurs in a wiring layer, the wiring layer is removed up to an element isolation region which is an element layer and then the wiring layer is reconstructed. There is. Since this technique is to reuse the element isolation region, it has a temporary effect in shortening the time until feedback of the effect confirmation for defects.

[0005]

However, the reuse from element isolation causes a problem that the multilayer wiring process must be rebuilt from the beginning. Therefore, the effect of shortening the time until feedback for early yield improvement cannot be sufficiently exerted. In addition, considering the application to the ultra-multilayer wiring semiconductor device, since the wiring region covers multiple layers, it is difficult to remove all the wiring layers with high accuracy.

One of the main objects of the present invention is to find a defective wiring layer in a subsequent step, thereby facilitating the removal up to the defective wiring layer and reconstructing the wiring layer. By doing so, it is to provide a manufacturing method that improves the manufacturing yield and shortens the time required for feedback.

[0007]

According to the present invention, there is provided a semiconductor device including an element formed on a semiconductor substrate and a multi-layer wiring layer formed on the semiconductor substrate and electrically connected to the element. A step of forming a test element for inspecting a defective wiring layer on a part of the semiconductor substrate, and a step of forming one or several wiring layers connected to the test element and simultaneously forming a pad for inspection. Immediately after forming one or several wiring layers, a step of inspecting the wiring layers by using pads and test elements, and a defective wiring when the wiring layers are inspected by the inspection The method is characterized by including a step of removing the layer and a step of re-forming the removed wiring layer.

In a preferred embodiment of the present invention, a plurality of test elements are formed, a plurality of wiring layers are assigned to each test element in a predetermined number, and the assigned wiring layers are inspected by using the test elements. I will do it. in this case,
Pads are formed on the plurality of wiring layers assigned to each test element to perform an inspection with the test element. For example, the test element is composed of an SRAM test element, and the wiring layer assigned to each test element is composed of three layers of a cell wire, a word line and a bit line.

According to another aspect of the present invention, the test element is composed of a wiring test element, a plurality of wiring layers are all assigned to the wiring test element, and all the wiring layers are individually inspected by the test element. Pad for forming.

According to the present invention, when manufacturing an ultra-multilayered wiring semiconductor device, a wiring step and its inspection step are sequentially performed for every one to several wiring layers, and finally a desired ultra-multilayered wiring is manufactured. You can Then, when a defect occurs in each of the manufactured vias and wiring layers in each wiring process, the wiring layer is immediately removed, and the wiring layer is manufactured again by wiring the defective wiring layer to the upper layer. It is possible to prevent the formation of a layer and to reduce the yield of the semiconductor device by removing the defective wiring layer and rebuilding the wiring layer.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a flow chart conceptually showing the technical idea of the present invention. In the manufacturing process of a semiconductor device, a wiring defect in a wiring layer is inspected, and if a wiring defect is detected, the wiring layer is reconstructed. The manufacturing process flow to do is shown. As shown in the figure, a base process S100 for forming a required semiconductor element on a semiconductor substrate is performed, but at this time, a plurality of test elements are formed simultaneously with the element. Then, a first wiring step S101 for forming an interlayer insulating film, a via, and a wiring layer on the base to electrically connect to the semiconductor element and configure a required circuit is performed. At this time, at least one test element is used. For the above, a test circuit is formed by the wiring layer in the first wiring step, and a test pad is formed on a part of the uppermost wiring layer. Next, the test pad is brought into contact with a probe or the like of an inspection machine, the test element is inspected, and then the first inspection step S102 of detecting a defect in the wiring layer in the first wiring step is executed. The result of the first inspection process is determined (S103), and if a wiring defect is detected, the wiring layer formed in the first wiring process is subjected to CMP (Chemical Mech.
It is removed by the anical Polishing method (S104), and the first wiring step S101 and its inspection step S102 are performed again.

When no wiring defect is detected in the first determination step S103, the second wiring step S201 is executed, and the second inspection step S202 is similarly executed. When a wiring defect is detected in the determination step S203, the wiring layer formed in the second wiring step S201 is removed by the CMP method, and the second wiring step S201 and its inspection step S20 are performed again.
Execute 2. If no wiring defect is detected in the second determination step S203, the third wiring step, the third inspection step, and the third determination step are executed in the same manner, although not shown in the figure. Thereafter, this step is sequentially executed, and finally the nth
The wiring step S301 and its inspection step S302 are executed,
When a wiring defect is detected in the nth determination step S303, the CMP step S304 is executed and the nth wiring step S3 is performed again.
01, nth inspection step S302 is performed, and if no defect is detected, it is determined that a desired wiring is formed, and a product inspection S400 of the semiconductor device is performed.

By forming the wiring in such a process, when manufacturing the ultra-multilayer wiring semiconductor device, the wiring process and its inspection process are sequentially performed for each wiring layer having a required number of layers, and the final purpose is obtained. Super multilayer wiring can be manufactured. Then, when a defect occurs in each of the manufactured vias and wiring layers in each wiring process, the wiring layer is immediately removed, and the wiring layer is manufactured again by wiring the defective wiring layer to the upper layer. The formation of layers is prevented. By doing so, defects such as dust, scratches, and problems due to parameters of the manufacturing apparatus, which are generated in the manufacturing process of each wiring layer, can be found in the process of the manufacturing process before the product is completed. Therefore, by removing the defective wiring layer and rebuilding the layer, it is possible to reduce the product yield reduction due to dust, scratches, etc., and shorten the time required for feedback before rebuilding. become.

FIG. 2 is a schematic plan view of a part of the chip in the first embodiment of the semiconductor device manufactured according to the present invention, in which a test element S is formed in a part of the empty area of the chip.
A configuration using a RAM test element is shown. Further, this embodiment shows an example of a semiconductor device in which 12 wiring layers are formed on a semiconductor element. That is, here, the wiring of 12 layers is divided into four groups A, B, C and D by three layers.
The SRAM test element A is arranged as the test element of the A group of the first layer to the third layer, and the SRAM test element B is arranged as the test element of the B group of the fourth layer to the sixth layer. The SRAM test element C is arranged as a test element of the C group of the seventh layer to the ninth layer,
SRA as a test element of the D group from the 12th layer to the 12th layer
The M test element D is arranged.

FIG. 3 is a schematic sectional view of the SRAM test elements A to D of each of the groups A, B, C and D. As shown in FIG. 2, the SRAM test elements A to D are formed on a part of the chip at the same time as the regular semiconductor elements not shown in the drawing. And S of A group
A required test circuit is configured by connecting the first to third wiring layers to the RAM test element A via the vias, and a test pad Pad is partially formed in the uppermost third wiring layer.
Is formed. Similarly, in the SRAM test element B of the B group, the wiring layers of the fourth to sixth layers are connected to the wiring layers of the first to third layers via the vias to form a required test circuit. A test pad Pad is formed on a part of the uppermost sixth wiring layer. Further, in the SRAM test element C of the C group, the wiring layers of 7th to 9th layers are connected to the wiring layers of the 1st to 6th layers through the vias to form a required test circuit. 9th of the top layer
The test pad Pad is formed on a part of the wiring layer. Further, in the SRAM test element D of the D group, the wiring layers of the 10th to 12th layers are connected to the wiring layers of the 1st to 9th layers through the vias to form a required test circuit. A test pad Pad is formed on a part of the uppermost twelfth wiring layer.

Here, in FIG. 3, the first, fourth, seventh and tenth layers which are the lowermost wiring layers of each group are cell wires,
The intermediate wiring layers 2, 5, 8 and 11 are word lines, and the upper wiring layers 3, 6, 9 and 12 are bit lines. Also, in the figure,
Although the via connection is not shown for the 9th and 12th layers, electrical connection is made to the SRAM test elements A, B, C, D at other locations not shown in the figure. Needless to say.

An example in which the manufacturing method of the present invention shown in FIG. 1 is applied to the semiconductor device manufactured in this manner is shown in FIG.
Will be described with reference to. First, after the wiring layers of the first layer to the third layer are formed, the inspection of the wiring layers of the first layer to the third layer is executed using the SRAM test element of the A group. In this inspection, for example, bitmap analysis of SRAM is executed. Here, no defect has occurred in the wiring layer, and therefore the wiring layers of the fourth to sixth layers are formed thereon. Next, the inspection of the wiring layers of the fourth layer to the sixth layer is executed by using the SRAM test element of the B group. If there is a defect in the fifth wiring layer, a wiring defect is detected in the inspection. Then, by performing the above-described bitmap analysis for the wiring failure, it can be detected that the wiring failure exists in the fifth wiring layer.

When a wiring defect in the fifth wiring layer is detected, it is possible to determine whether the cause of the defect affects the overall yield by performing the same measurement on the entire surface of the wafer. Based on the results, CMP is performed on the semiconductor device at a level that affects the overall yield.
The surface is polished by a method to remove the sixth and fifth wiring layers. After the removal, the fifth wiring layer and the sixth wiring layer
Re-manufacture the wiring layer of the second layer, and again use the SRA of the B group.
The inspection of the fourth to sixth wiring layers is performed using the M test element. Hereinafter, similarly, the wiring layers from the seventh layer to the ninth layer,
With respect to the tenth to twelfth wiring layers as well, the manufacturing up to the final wiring layer of the twelfth layer is performed while sequentially performing manufacturing and wiring failure.

As described above, since the manufacturing process is performed while eliminating the cause of defects in the wiring process, it can be seen that, unlike the conventional manufacturing method, the defective rate in the wiring process is significantly reduced. In addition, in the present embodiment, when the cause of the defect is generated in the fifth wiring layer, the defect is confirmed by the inspection after the manufacturing process of the sixth wiring layer, so that the wiring layers of all 12 wiring layers are confirmed. Compared with post-manufacturing inspection, it takes less time to find the cause of the defect, and the time required for remanufacturing can be shortened. To be

Further, in this embodiment, the SRAM test element is used as the wiring failure determination element, and the analysis result of the SRAM bitmap is determined as the wiring failure rate. By using such a method, it is possible to see the difference in the defective rate of the bit map even within the same element, and thus it is possible to obtain an advantage that the degree of influence of the defective on the entire wafer can be known in detail. Further, in this embodiment, since the step of removing the defective wiring by the CMP method and rebuilding is adopted immediately after the wiring step in which the defect occurs, the wiring layer to be removed even when the wiring layer is removed by CMP. Is 3 layers or less at the maximum, CM from the top layer
Compared with polishing with P, there is an advantage that uniform polishing can be easily performed. further,
In this embodiment, the wiring layers for three layers can be evaluated at the same time by utilizing the difference in the defective mode of the bit line, the word line, and the cell wire of the SRAM test element as the evaluation element of each wiring layer. Therefore, since the wiring layer evaluation process may be performed every three layers, there is an advantage that the number of evaluation steps can be reduced.

In the first embodiment, the SRAM test element is used as the evaluation element of the wiring layer of the present invention, but this can be applied to other wiring test elements.
Further, in the above-described embodiment, the CMP method is used as the wiring removal method, but a wiring removal method by wet etching can also be used. 5 and 6 show the second embodiment, FIG. 5 is a plan view of a part of the chip, and FIG. 6 is a schematic sectional view. In FIG. 5, the wiring test element E capable of inspecting the wiring short-circuit / open of each layer of the ultra-multilayer wiring is vacant in the chip so as to cover all wiring layers as in the case of using the SRAM test element. Placed in a part of.

As shown in FIG. 6, the wiring test device E
First to twelfth wiring layers forming the super multi-layer wiring are sequentially formed on the upper side in a stacked state, and a pad Pad is formed in each wiring layer. In this embodiment, every time one wiring layer from the first layer to the twelfth layer is formed, the inspection is performed using the pads Pad of each wiring layer. Then, if a defect is detected in the inspection and the defect rate is high in the entire wafer, the wiring layer is removed by wet etching, and the wiring layer is reconstructed again.

By doing so, in the second embodiment, the defect of the wiring layer is inspected for each layer, the defect rate of each wiring layer is measured for each layer, and then the wiring layer is wet-etched. In order to determine whether the wiring is to be removed, only one layer needs to be removed. Therefore, it is possible to obtain an effect that the wiring can be removed more easily than when the SRAM test element of the first embodiment is used.

Here, in the wiring test element E used as the wiring evaluation element, the wiring test element can be divided into a plurality of regions and the degree difference can be investigated so that the degree difference of the defective rate can be sufficiently confirmed. It is better to use such a structure.
Further, although the short / open test element of the wiring is used, the defect rate of the via can be determined by using the test element of the via chain at the same time, so that the defect rate of the via can be reduced. Furthermore, the same effect can be obtained by replacing the wiring evaluation element of the second embodiment with the above-described element that can evaluate the defect rate of the wiring.

FIG. 7 is a plan view of a part of the chip according to the third embodiment of the present invention. In the first embodiment, the SRAM test elements A to D are used as the wiring determination elements.
The peripheral circuit F of the SRAM test element is connected to each SRA in the chip.
It can be configured to be shared with the M element. In the present embodiment, the cell portion inside one SRAM test element is divided into banks, and the first test area is divided into the first and second SRAM test elements as in the SRAM test element.
The SRAM test elements of groups A, B, C, and D are arranged so as to cover the wiring layers from the layer to the twelfth layer. Then, for each SRAM test element of each group A, B, C, D, three pads are provided so that each wiring layer can be inspected during the manufacturing process using each SRAM test element as shown in FIG. Place every other layer.

In the present embodiment, when the wiring layer is inspected during the manufacturing process, the banks are switched to perform the inspection by each SRAM test element, and the defect rate is measured, so that the same as in the first embodiment. It is possible to detect the defective rate of the wiring, and by removing and rebuilding the defective wiring layer from the result, it is possible to reduce the yield reduction of the wiring. Further, in this embodiment, the peripheral circuit is shared by the SRAM test element and the SRAM element of the internal circuit, so that the space required for arranging each SRAM element can be reduced. In addition, since the influence of the defect in the peripheral circuit unit is unified in each SRAM element by sharing the peripheral circuit, the synergistic effect that the wiring can be evaluated under the condition that the influence of the defect in the peripheral circuit unit is not exerted. Has a great effect.

[0027]

As described above, according to the present invention, when manufacturing a semiconductor device having multi-layer wiring, the wiring step and its inspection step are sequentially performed for every one to several wiring layers, and finally the target multi-layer is obtained. Since a semiconductor device having a wiring structure is manufactured, when a defect occurs in the via or wiring layer manufactured in each wiring step, the wiring layer is immediately removed, and the defective wiring layer is manufactured by manufacturing the wiring layer again. Since it is possible to prevent the wiring layer from being formed on the upper layer of the semiconductor device as it is left, it is possible to reduce the reduction in the yield of the semiconductor device and to shorten the time until feedback by reconstruction.

[Brief description of drawings]

FIG. 1 is a process flow chart showing an example of a manufacturing process of the present invention.

FIG. 2 is a layout diagram of an SRAM test element according to the first embodiment of the present invention.

3 is a schematic cross-sectional view of a wiring layer on each SRAM test element of FIG.

FIG. 4 is a schematic diagram for explaining a manufacturing process of the first embodiment.

FIG. 5 is a layout view of a wiring test element according to a second embodiment of the present invention.

6 is a schematic cross-sectional view of a wiring layer on the wiring test element of FIG.

FIG. 7 is a layout diagram of an SRAM test element according to a third embodiment of the present invention.

[Explanation of symbols]

A to D SRAM test element E Wiring test element F peripheral circuit

Claims (7)

[Claims] 1. A semiconductor device comprising an element formed on a semiconductor substrate and a multilayer wiring layer formed on the semiconductor substrate and electrically connected to the element, wherein the semiconductor substrate of the semiconductor substrate is formed when the element is formed. A step of forming a test element for inspecting a defect of the wiring layer on a part thereof; a step of forming one or several wiring layers connected to the test element and simultaneously forming a pad for inspection; A step of inspecting the wiring layer by using the pad and the test element after forming one to several wiring layers; and a case where the wiring layer is inspected as a defective wiring by the inspection. A method of manufacturing a semiconductor device, comprising: a step of removing a wiring layer; and a step of forming the removed wiring layer again. 2. A plurality of the test elements are formed, the plurality of wiring layers are assigned to each of the test elements in a predetermined number, and the assigned wiring layers are inspected by using the test elements. The method for manufacturing a semiconductor device according to claim 1, wherein the method is for manufacturing a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 2, wherein a pad for performing an inspection with the test element is formed on a plurality of wiring layers assigned to each test element. . 4. The test element is composed of an SRAM test element, and a wiring layer assigned to each test element is composed of three layers of a cell wire, a word line and a bit line. A method for manufacturing a semiconductor device as described above. 5. The test element is composed of a wiring test element, a plurality of wiring layers are allotted to the wiring test element, and a pad for performing an inspection by the test element is formed on each of the wiring layers. The method of manufacturing a semiconductor device according to claim 2, wherein 6. The element formed on the semiconductor substrate is SR
5. The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is an AM element, and the SRAM element and the SRAM test element share a peripheral circuit. 7. The step of removing the defective wiring is CMP.
7. The method of manufacturing a semiconductor device according to claim 1, wherein the method is a (chemical mechanical polishing) method or an etching method.