CN117672888A - Semiconductor structure, formation method and layout design method, circuit and working method - Google Patents

Abstract

A semiconductor structure, formation method, layout design method, circuit and working method. The structure includes: a substrate, the substrate includes a middle region and an edge region located around the middle region; a plurality of layers of vertically stacked layers located on the middle region. a metal layer and a second metal layer, the first metal layer is parallel to the first direction, the second metal layer is parallel to the second direction, the first direction and the second direction are parallel to the substrate surface, and the The first direction and the second direction are perpendicular to each other; there are several connected edge circuit units located in the edge area, the edge circuit units include short-circuit units or open-circuit units, the edge circuit units include at least one layer of metal structure, the metal The structure is parallel to the first metal layer, and the top surface of the metal structure is flush with the top surface of the first metal layer. The semiconductor structure improves chip utilization.

Description

Semiconductor structure, formation method and layout design method, circuit and working method

Technical field

The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure, a forming method, a layout design method, a circuit and a working method.

Background technique

As the size of semiconductor process nodes shrinks, the size and spacing of metal, through-hole and other structures are also reduced, and many new processes are introduced to prepare these structures, such as self-aligned multiple exposure technology (Self-Align Double/ Quadruple Pattern (SADP/SAQP for short). These processes are very complex and have many line-end defects, which correspond to the edges of the chip. Therefore, a blank margin area needs to be left at the edge of the chip to ensure that the internal Normal operation of edge areas.

There are two effects of these defects on the circuit. One is that the disconnected structure in the design is short-circuited. The reason may be that the originally unconnected metals are connected due to defects. The other is that the connected structure in the design is disconnected. The reason may be that the metal is missing during processing, or the via hole is not in contact with the metal, etc.

Leaving blank margins at the edges of the chip will increase the area of the chip. For some complex chips with large storage capacity, the additional area increase caused by these blank margins is considerable.

Therefore, process monitoring at the edge of the chip is very important.

Contents of the invention

The technical problem solved by the present invention is to provide a semiconductor structure, formation method, layout design method, circuit and working method to monitor the process of the chip edge.

In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate includes a middle region and an edge region located around the middle region; several layers of vertically stacked first metals located on the middle region. layer and a second metal layer, the first metal layer is parallel to the first direction, the second metal layer is parallel to the second direction, the first direction and the second direction are parallel to the substrate surface, and the third One direction and the second direction are perpendicular to each other; several connected edge circuit units located in the edge area, the edge circuit units include short-circuit units or open-circuit units, the edge circuit units include at least one layer of metal structure, the metal structure and The first metal layer is parallel, and the metal structure is flush with the top surface of the first metal layer.

Optionally, a plurality of the edge circuit units are located on edge areas on both sides of the middle area along the first direction, and a plurality of the edge circuit units are arranged in the edge area along the second direction.

Optionally, the edge circuit unit includes a short-circuit unit; the metal structure includes: a first input terminal, a first output terminal, a first power terminal, a first ground terminal and a plurality of third metal layers; the short-circuit unit also It includes: a first plug located on the third metal layer, the first input terminal or the first output terminal, a first connection layer located on the first plug, the first connection layer is perpendicular to the third metal layer ; The first connection layer is electrically connected to the first input terminal, the first output terminal and a plurality of third metal layers, and the circuit between the first input terminal and the first output terminal is a short circuit circuit.

Optionally, several short-circuit units are connected in series, and the first input terminal of the previous short-circuit unit is connected to the first output terminal of the subsequent short-circuit unit.

Optionally, the first input terminal of the previous short-circuit unit and the first output terminal of the subsequent short-circuit unit are connected through a first wiring unit, and the first wiring unit includes: a first wiring connected to the first input terminal. layer, a second wiring layer connected to the first output terminal, a third wiring layer electrically connected to the first wiring layer and the second wiring layer, the first wiring layer and the second wiring layer and the first metal layer Parallel, the third wiring layer is parallel to the first connection layer.

Optionally, the first wiring unit further includes: a fourth power terminal connected to the first power terminal, and a fourth ground terminal connected to the first ground terminal, the fourth power terminal and the fourth ground terminal The end is parallel to the first metal layer.

Optionally, it also includes: a fifth power terminal and a fifth ground terminal located on the middle area, the fifth power terminal and the fifth ground terminal being parallel to the first direction; the first power terminal passing through the first wiring unit It is connected to the fifth power terminal of the middle area, and the first ground terminal is connected to the fifth ground terminal of the middle area through the first wiring unit.

Optionally, the edge circuit unit includes an open-circuit unit; the metal structure includes: a second power terminal, a second ground terminal and several alternately arranged fourth and fifth metal layers; the open-circuit unit also includes: a second plug located on the fourth metal layer and on the second power terminal, a third plug located on the fifth metal layer and the second ground terminal, a second connection layer located on the second plug, The third connection layer on the three plugs, the fourth metal layer and the second connection layer are vertical, the fifth metal layer and the third connection layer are vertical; the second connection layer is electrically connected to the fourth metal layer and the third connection layer. Two power terminals, the third connection layer is electrically connected to the fifth metal layer and the second ground terminal, and the circuit between the second ground terminal and the second power terminal is an open circuit.

Optionally, several open-circuit units are connected in a parallel manner, with the second power terminals of several open-circuit units connected to each other and the second ground terminals of several open-circuit units connected to each other.

Optionally, several open-circuit units are connected through a second wiring unit. The second wiring unit includes: a fourth wiring layer connected to the second power terminal, a fifth wiring layer connected to the second ground terminal, and a fourth wiring layer connected to the second ground terminal. The sixth wiring layer is connected to a plurality of fourth wiring layers, and the seventh wiring layer is electrically connected to a plurality of fifth wiring layers. The fourth wiring layer and the fifth wiring layer are parallel to the first metal layer, and the sixth wiring layer and The seventh wiring layer is parallel to the second connection layer.

Optionally, it also includes: a fifth power terminal and a fifth ground terminal located on the middle area, the fifth power terminal and the fifth ground terminal being parallel to the first direction; the second power terminal passing through the second wiring unit It is connected to the fifth power terminal of the middle area, and the second ground terminal is connected to the fifth ground terminal of the middle area through the second wiring unit.

Optionally, it also includes: several filling units, the filling units are used to fill the gaps in the edge area, the filling units include: a third power terminal and a third ground terminal, the third power terminal and the third ground terminal Parallel to the first metal layer, the third power terminal is connected to the first power terminal, and the third ground terminal is connected to the first ground terminal.

Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate including a middle region and an edge region located around the middle region; forming several vertically stacked layers on the middle region. a metal layer and a second metal layer, the first metal layer is parallel to the first direction, the second metal layer is parallel to the second direction, the first direction and the second direction are parallel to the substrate surface, and the The first direction and the second direction are perpendicular to each other; several connected edge circuit units are formed on the edge area, the edge circuit units include short-circuit units or open-circuit units, the edge circuit units include at least one layer of metal structure, The metal structure is parallel to the first metal layer, and a top surface of the metal structure is flush with a top surface of the first metal layer.

Optionally, the metal structure and the first metal layer are formed at the same time; a plurality of the edge circuit units are located on the edge areas on both sides of the middle area along the first direction, and a plurality of the edge circuit units are located on the edge area along the first direction. Arranged in two directions.

Optionally, the edge circuit unit includes a short-circuit unit; the metal structure includes: a first input terminal, a first output terminal, a first power terminal, a first ground terminal and a plurality of third metal layers; the short-circuit unit also It includes: a first plug located on the third metal layer, the first input terminal or the first output terminal, a first connection layer located on the first plug, the first connection layer is perpendicular to the third metal layer ; The first connection layer is electrically connected to the first input terminal, the first output terminal and a plurality of third metal layers, and the circuit between the first input terminal and the first output terminal is a short circuit circuit.

Optionally, several short-circuit units are connected in series, and the first input terminal of the previous short-circuit unit is connected to the first output terminal of the subsequent short-circuit unit.

Optionally, the first input terminal of the previous short-circuit unit and the first output terminal of the subsequent short-circuit unit are connected through a first wiring unit, and the first wiring unit includes: a first wiring connected to the first input terminal. layer, a second wiring layer connected to the first output terminal, a third wiring layer electrically connected to the first wiring layer and the second wiring layer, the first wiring layer and the second wiring layer and the first metal layer Parallel, the third wiring layer is parallel to the first connection layer.

Optionally, the first connection layer and the second metal layer are formed simultaneously.

Optionally, the edge circuit unit includes an open-circuit unit; the metal structure includes: a second power terminal, a second ground terminal and several alternately arranged fourth and fifth metal layers; the open-circuit unit also includes: a second plug located on the fourth metal layer and on the second power terminal, a third plug located on the fifth metal layer and the second ground terminal, a second connection layer located on the second plug, The third connection layer on the three plugs, the fourth metal layer and the second connection layer are vertical, the fifth metal layer and the third connection layer are vertical; the second connection layer is electrically connected to the fourth metal layer and the third connection layer. Two power terminals, the third connection layer is electrically connected to the fifth metal layer and the second ground terminal, and the circuit between the second ground terminal and the second power terminal is an open circuit.

Optionally, several open-circuit units are connected in a parallel manner, with the second power terminals of several open-circuit units connected to each other and the second ground terminals of several open-circuit units connected to each other.

Optionally, several open-circuit units are connected through a second wiring unit. The second wiring unit includes: a fourth wiring layer connected to the second power terminal, a fifth wiring layer connected to the second ground terminal, and a fourth wiring layer connected to the second ground terminal. The sixth wiring layer is connected to a plurality of fourth wiring layers, and the seventh wiring layer is electrically connected to a plurality of fifth wiring layers. The fourth wiring layer and the fifth wiring layer are parallel to the first metal layer, and the sixth wiring layer and The seventh wiring layer is parallel to the second connection layer.

Optionally, the second connection layer and the third connection layer are formed simultaneously with the second metal layer.

Optionally, it also includes: forming several filling units, the filling units being used to fill the gaps in the edge area, the filling units including: a third power terminal and a third ground terminal, the third power terminal and the third ground terminal. The end is parallel to the first metal layer.

Correspondingly, the technical solution of the present invention also provides an edge monitoring circuit, including: several connected edge circuit units.

Optionally, the edge circuit unit includes a short-circuit unit; several short-circuit units are connected in series.

Optionally, the short-circuit unit includes a first input terminal and a first output terminal, and the circuit between the first input terminal and the first output terminal is a short-circuit circuit; the first input terminal of the previous short-circuit unit and the subsequent one The first output terminal of the short circuit unit is connected.

Optionally, the edge circuit unit includes an open circuit unit; several open circuit units are connected in parallel.

Optionally, the open-circuit unit includes: a second power terminal and a second ground terminal, and the circuit between the second ground terminal and the second power terminal is an open-circuit circuit; the second power terminals of several open-circuit units are connected, and several The second ground connection of the open circuit unit.

Correspondingly, the technical solution of the present invention also provides a working method of an edge monitoring circuit, which includes: providing an edge monitoring circuit, and the edge monitoring circuit includes: a plurality of connected edge circuit units; after the edge monitoring circuit is powered on, it determines whether the edge monitoring Whether the circuit is in a short circuit or open circuit state; according to the state of the edge monitoring circuit, it is judged whether the edge monitoring circuit is normal. If the edge monitoring circuit is abnormal, the edge monitoring circuit is inspected.

Optionally, the edge circuit unit includes a short-circuit unit; according to the state of the edge monitoring circuit, the method for determining whether the edge monitoring circuit is normal includes: if the edge monitoring circuit is in a short-circuit state, the edge monitoring circuit is normal; If the edge monitoring circuit is in an open circuit state, the edge monitoring circuit is abnormal and the edge monitoring circuit needs to be inspected and repaired.

Optionally, the edge circuit unit includes an open circuit unit; according to the state of the edge monitoring circuit, the method for determining whether the edge monitoring circuit is normal includes: if the edge monitoring circuit is in an open circuit state, the edge monitoring circuit is normal; If the edge monitoring circuit is in a short-circuit state, the edge monitoring circuit is abnormal, and the edge monitoring circuit needs to be repaired.

Correspondingly, the technical solution of the present invention also provides a semiconductor layout design method, including: layout, the layout includes a middle area and an edge area located around the middle area; providing edge circuit units; and arranging several connected edge circuits in the edge area. unit.

Optionally, the edge circuit unit includes a short-circuit unit; several short-circuit units are connected in series.

Optionally, the edge circuit unit includes an open-circuit unit; the open-circuit units are connected in parallel.

Compared with the existing technology, the technical solution of the present invention has the following beneficial effects:

In the semiconductor structure of the technical solution of the present invention, several connected edge circuit units are provided on the edge area. Since the structure of the edge circuit unit is known, the environment at the edge of the chip can be well realized, which is conducive to studying edge defects. At the same time, the circuits on the edge of the chip can also be used to improve chip area utilization; in addition, the edge circuit unit The structure is repetitive, so the layout and wiring at the edge of the chip is convenient and can be constrained with fewer design rules, that is, a scannable and testable circuit for the edge structure can be realized; the edge circuit unit has a simple structure, so it has strong applicability. As long as it conforms to the standard digital unit architecture, this circuit measurement back-end process can be used, and it is suitable for all nodes of mature processes and advanced processes.

Further, several of the edge circuit units are connected through the first wiring unit or the second wiring unit. The wiring unit is separated from the edge circuit unit, and the environment of the chip edge structure can be reproduced better without being disturbed and affected by the test circuit.

Further, the first power terminal is connected to the fifth power terminal in the middle area through the first wiring unit, the first ground terminal is connected to the fifth ground terminal in the middle area through the first wiring unit, and the second power terminal is connected through the second wiring. The unit is connected to the fifth power terminal of the middle area, and the second ground terminal is connected to the fifth ground terminal of the middle area through the second wiring unit. Therefore, non-edge areas such as the middle area of the chip can also be scanned and studied, so that the chip area is not wasted.

The working method of the edge monitoring circuit of the technical solution of the present invention determines whether the edge monitoring circuit is normal. If the edge monitoring circuit is abnormal, the edge monitoring circuit is inspected and repaired. If the edge monitoring circuit is normal, use the edge monitoring circuit.

Description of drawings

1 to 4 are top views of a semiconductor structure in an embodiment of the present invention;

5 to 7 are top views of a semiconductor structure in another embodiment of the present invention;

Figures 8 to 10 are schematic diagrams of an edge monitoring circuit in an embodiment of the present invention;

Figures 11 to 13 are schematic diagrams of an edge monitoring circuit in another embodiment of the present invention;

Figure 14 is a schematic flow chart of the working method of the edge monitoring circuit in the embodiment of the present invention;

FIG. 15 is a schematic flowchart of a semiconductor layout design method in an embodiment of the present invention.

Detailed ways

As mentioned in the background, process monitoring at the chip edge is very important.

Specifically, a large part of the process monitoring at the edge of the chip is the metal and via holes in the middle and back-end processes. The detection content is open circuit and short circuit. Therefore, the test circuit is relatively simple, and the corresponding number of layers prepared in the process is also small, usually Two metal layers and one via layer, such as Metal1, Metal2 and Via1. In this way, the manufacturing process is relatively simple and processing and testing can be completed quickly. But the disadvantage is that because there is no front-end process, addressable circuits that require transistors cannot be designed.

In the traditional method, designers need to realize various structures that generate defects through layout, while simulating the environment around the defects in a certain area and trying to change the environment. To further study the probability of defects in a certain structure, it is necessary to repeat such structures in large numbers and measure their open or short circuit states through circuits. However, a large number of repetitions of structures will lead to changes in the edge environment of the original design, and the boundaries of the chip may no longer be boundaries. At the same time, there are many types of defects at the chip boundary, the environment is complex, and it is highly dependent on the experience of designers. It is necessary to design, layout and route one by one, and the design efficiency is low.

In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure, a forming method, a layout design method, a circuit and a working method, in which a plurality of connected edge circuit units are provided on the edge area. Since the structure of the edge circuit unit is known, the environment at the edge of the chip can be well realized, which is conducive to studying edge defects. At the same time, the circuits on the edge of the chip can also be used to improve chip area utilization; in addition, the edge circuit unit The structure is repetitive, so the layout and wiring at the edge of the chip is convenient and can be constrained with fewer design rules, that is, a scannable and testable circuit for the edge structure can be realized; the edge circuit unit has a simple structure, so it has strong applicability. As long as it conforms to the standard digital unit architecture, this circuit measurement back-end process can be used, and it is suitable for all nodes of mature processes and advanced processes.

In order to make the above objects, features and beneficial effects of the present invention more obvious and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

1 to 4 are top views of a semiconductor structure according to an embodiment of the present invention.

Referring to FIG. 1 , a substrate 100 is provided, which includes a middle region I and an edge region II located around the middle region I.

The edge area II surrounds the middle area I, and the figure only shows part of the edge area II located in the first direction X.

Please continue to refer to Figure 1. Several layers of vertically stacked first metal layers (not shown) and second metal layers (not shown) are formed on the middle area I, and the first metal layers are parallel to the first direction X, The second metal layer is parallel to the second direction Y, the first direction X and the second direction Y are parallel to the surface of the substrate 100 , and the first direction X and the second direction Y are perpendicular to each other.

The first direction X and the second direction Y are the horizontal and vertical directions fixed during semiconductor layout design. Based on the settings of these directions, the direction design of the first metal layer and the second metal layer in the semiconductor structure is also The design rules need to be met, that is, the first metal layer needs to be parallel to the first direction X, and the second metal layer needs to be parallel to the second direction Y.

In this embodiment, the method further includes: forming a fifth power terminal 120 and a fifth ground terminal 121 parallel to the first direction X on the middle region I.

Please continue to refer to Figures 1 and 2. Figure 2 is a schematic structural diagram of a single edge circuit unit in Figure 1. Several connected edge circuit units are formed on the edge area II. The edge circuit units include one or more layers of metal structures. , the metal structure is parallel to the first metal layer, and the top surface of the metal structure is flush with the top surface of the first metal layer. The edge circuit unit is used to monitor product defects.

In this embodiment, the metal structure and the first metal layer are formed simultaneously.

A plurality of the edge circuit units are located on the edge areas II on both sides of the middle area I along the first direction X, and a plurality of the edge circuit units are arranged along the second direction Y on the edge area II.

In this embodiment, the edge circuit unit includes a short-circuit unit. The short-circuit unit is a unit of the short-circuit circuit.

In this embodiment, the metal structure includes: a first input terminal 101, a first output terminal 102, a first power terminal 103, a first ground terminal 104 and a plurality of third metal layers 105.

In this embodiment, the first power terminal 103 is connected to the fifth power terminal 120 of the middle region I through the first wiring unit, and the first ground terminal 104 is connected to the fifth power terminal 120 of the middle region I through the first wiring unit. The ground terminal 121 is connected. Therefore, non-edge areas such as the middle area of the chip can also be scanned and studied, so that the chip area is not wasted.

In this embodiment, the short-circuit unit further includes: a first plug (not shown) located on the third metal layer 105, on the first input terminal 101 or on the first output terminal 102. The first connection layer 106 is perpendicular to the third metal layer 105 .

In this embodiment, the first connection layer 106 and the second metal layer are formed simultaneously.

The first connection layer 106 is electrically connected to the first input terminal 101, the first output terminal 102 and a plurality of third metal layers 105. The circuit between the first input terminal 101 and the first output terminal 102 is a short circuit circuit.

In this embodiment, several short-circuit units are connected in series, and the first input terminal 101 of the previous short-circuit unit is connected to the first output terminal 102 of the subsequent short-circuit unit.

Please refer to Figures 1 and 3. Figure 3 is a schematic structural diagram of a single first wiring unit in Figure 1. In this embodiment, the first input terminal 101 of the previous short-circuit unit and the first output terminal 102 of the subsequent short-circuit unit Connected through a first wiring unit, the first wiring unit includes: a first wiring layer 110 connected to the first input terminal 101, a second wiring layer 111 connected to the first output terminal 102, electrically connected to the The first wiring layer 110 and the third wiring layer 112 of the second wiring layer 111 are parallel to the first metal layer, and the third wiring layer 112 is connected to the first connection layer. 106 parallel.

The third wiring layer 112 located at both ends of the second direction Y is respectively connected to an external circuit for pressurization to monitor the effect of the series connection of several short-circuit units.

Please continue to refer to Figures 1 and 3. In this embodiment, the first wiring unit further includes: a fourth power terminal 113 connected to the first power terminal 103, and a third power terminal 113 connected to the first ground terminal 104. Four ground terminals 114, the fourth power terminal 113 and the fourth ground terminal 114 are parallel to the first metal layer.

In this embodiment, the first power terminal 103 is connected to the fifth power terminal 120 of the middle area I through the fourth power terminal 113 of the first wiring unit, and the first ground terminal 104 is connected through the fourth power terminal 113 of the first wiring unit. The fourth ground terminal 114 is connected to the fifth ground terminal 121 of the middle region I. Therefore, non-edge areas such as the middle area of the chip can also be scanned and studied, so that the chip area is not wasted.

The first wiring unit is separated from the short-circuit unit, and the environment of the chip edge structure can be reproduced better without being disturbed and affected by the test line.

Please refer to Figures 1 and 4. Figure 4 is a schematic structural diagram of a single filling unit. The method of forming the semiconductor structure also includes: forming a number of filling units. The filling units are used to fill the gaps in the edge region II. The filling units It includes: a third power terminal 130 and a third ground terminal 131, the third power terminal 130 and the third ground 131 are parallel to the first metal layer, and the third power terminal 130 is connected to the first power terminal 103, The third ground terminal 131 is connected to the first ground terminal 104 .

The third power terminal 130 and the third ground terminal 131 are formed simultaneously with the first metal layer.

Correspondingly, embodiments of the present invention also provide a semiconductor structure as shown in FIGS. 1 to 4 .

Several connected edge circuit units are arranged on the edge area II. Since the structure of the edge circuit unit is known, the environment at the edge of the chip can be well realized, which is conducive to studying edge defects. At the same time, the circuits on the edge of the chip can also be used to improve chip area utilization; in addition, the edge circuit unit The structure is repetitive, so the layout and wiring at the edge of the chip is convenient and can be constrained with fewer design rules, that is, a scannable and testable circuit for the edge structure can be realized; the edge circuit unit has a simple structure, so it has strong applicability. As long as it conforms to the standard digital unit architecture, this circuit measurement back-end process can be used, and it is suitable for all nodes of mature processes and advanced processes.

5 to 7 are top views of a semiconductor structure in another embodiment of the present invention.

Referring to FIG. 5 , a substrate 200 is provided, which includes a middle region I and an edge region II located around the middle region I.

The edge area II surrounds the middle area I, and the figure only shows part of the edge area II located in the first direction X.

Please continue to refer to Figure 5. Several layers of vertically stacked first metal layers (not shown) and second metal layers (not shown) are formed on the middle area I, and the first metal layers are parallel to the first direction X, The second metal layer is parallel to the second direction Y, the first direction X and the second direction Y are parallel to the surface of the substrate 200 , and the first direction X and the second direction Y are perpendicular to each other.

In this embodiment, the method further includes: forming a fifth power terminal 220 and a fifth ground terminal 221 parallel to the first direction X on the middle region I.

Please continue to refer to Figures 5 and 6. Figure 6 is a schematic structural diagram of a single edge circuit unit in Figure 5. Several connected edge circuit units are formed on the edge area II. The edge circuit units include one or more layers of metal structures. , the metal structure is parallel to the first metal layer, and the metal structure is flush with the top surface of the first metal layer.

In this embodiment, the metal structure and the first metal layer are formed simultaneously.

A plurality of the edge circuit units are located on the edge areas II on both sides of the middle area I along the first direction X, and a plurality of the edge circuit units are arranged along the second direction Y on the edge area II.

In this embodiment, the edge circuit unit includes an open circuit unit. The open-circuit unit is a unit of an open-circuit circuit.

In this embodiment, the metal structure includes: a second power terminal 201, a second ground terminal 202, and a plurality of alternately arranged fourth metal layers 203 and fifth metal layers 204.

In this embodiment, the open-circuit unit also includes: a second plug (not shown) located on the fourth metal layer 203 and the second power terminal 201, and a second plug (not shown) located on the fifth metal layer 204 and the second ground terminal. 202 on the third plug (not shown), the second connection layer 205 on the second plug, the third connection layer 206 on the third plug, the fourth metal layer 203 and the second connection layer The layer 205 is vertical, and the fifth metal layer 204 and the third connection layer 206 are vertical.

The second connection layer 205 is electrically connected to the fourth metal layer 203 and the second power terminal 201. The third connection layer 206 is electrically connected to the fifth metal layer 204 and the second ground terminal 202. The second ground terminal 202 and The circuit between the second power terminals 201 is an open circuit.

In this embodiment, several open-circuit units are connected in a parallel manner, with the second power terminals 201 of the several open-circuit units being connected, and the second ground terminals 202 of the several open-circuit units being connected.

Please refer to Figures 5 and 7. Figure 7 is a schematic structural diagram of a single second wiring unit in Figure 5. In this embodiment, several open circuit units are connected through the second wiring unit. The second wiring unit includes: The fourth wiring layer 207 connected to the two power terminals 201, the fifth wiring layer 208 connected to the second ground terminal 202, the sixth wiring layer 209 electrically connected to a plurality of fourth wiring layers 207, and the plurality of fifth wiring layers electrically connected. 208 of the seventh wiring layer 210, the fourth wiring layer 207 and the fifth wiring layer 208 are parallel to the first metal layer, and the sixth wiring layer 209 and the seventh wiring layer 210 are parallel to the second connection layer 205.

The sixth wiring layer 209 is electrically connected to the second power terminals 201 of a plurality of open-circuit units to connect and pressurize with an external power supply. The seventh wiring layer 210 is electrically connected to the second ground terminals 202 of a plurality of open-circuit units to be connected to an external power supply. The connection is pressurized to monitor the effect of parallel connection of several open circuit units.

The second wiring unit is separated from the open circuit unit, and the environment of the chip edge structure can be reproduced better without being interfered and affected by the test circuit.

In this embodiment, the second connection layer 205 and the third connection layer 206 are formed simultaneously with the second metal layer.

In this embodiment, the second power terminal 201 is connected to the fifth power terminal 220 in the middle area through the fourth wiring layer 207 of the second wiring unit, and the second ground terminal 202 is connected to the middle area through the second wiring unit. The fifth wiring layer 208 of the area is connected to the fifth ground terminal 221.

In this embodiment, it also includes: forming several filling units, the filling units being used to fill the gaps in the edge region II, the filling units including: a third power terminal and a third ground terminal, the third power terminal and The third ground is parallel to the first metal layer, the third power terminal is connected to the second power terminal 201 , and the third ground terminal is connected to the second ground terminal 202 .

Correspondingly, embodiments of the present invention also provide a semiconductor structure as shown in FIGS. 5 to 7 .

8 to 10 are schematic diagrams of an edge monitoring circuit in an embodiment of the present invention.

Please refer to Figures 8 to 10. Figure 8 is a schematic diagram of the edge monitoring circuit. Figure 9 is a circuit schematic diagram of the edge circuit unit in Figure 8. Figure 10 is a circuit schematic diagram of the first wiring unit in Figure 8, including: several connected Edge circuit unit.

In this embodiment, the edge circuit unit includes a short-circuit unit sample; several short-circuit unit samples are connected in series.

The short-circuit unit sample includes: a first input terminal IN and a first output terminal OUT. The circuit between the first input terminal IN and the first output terminal OUT is a short-circuit circuit. The short-circuit unit sample also includes a first power supply. terminal VDD1 and the first ground terminal VSS1; the first input terminal IN of the previous short-circuit unit is connected to the first output terminal OUT of the subsequent short-circuit unit.

The first input terminal IN of the previous short-circuit unit and the first output terminal OUT of the subsequent short-circuit unit are connected through a first wiring unit. The first wiring unit includes: a connected first terminal L1 and a second terminal L2, The first terminal L1 is connected to the first input terminal IN of the previous short-circuit unit, and the second terminal L2 is connected to the first output terminal OUT of the subsequent short-circuit unit.

In this embodiment, pad1 and pad2 are used to energize several edge circuit units connected in series.

The edge monitoring circuit is composed of several short-circuit units and a first wiring unit. The circuit structure is simple and the utilization rate is high.

11 to 13 are schematic diagrams of an edge monitoring circuit in another embodiment of the present invention.

Please refer to Figures 11 to 13. Figure 11 is a schematic diagram of the edge monitoring circuit. Figure 12 is a circuit schematic diagram of the edge circuit unit in Figure 11. Figure 13 is a circuit schematic diagram of the second wiring unit in Figure 11, including: several connected Edge circuit unit.

In this embodiment, the edge circuit unit includes an open-circuit unit sample; several open-circuit unit samples are connected in parallel.

The open-circuit unit sample includes: a second power terminal VDD and a second ground terminal VSS. The circuit between the second ground terminal VSS and the second power terminal VDD is an open-circuit circuit; the second power terminal VDD of several open-circuit unit samples connection, the second ground terminal VSS of several open-circuit unit samples is connected.

Several open-circuit unit samples are connected through a second wiring unit. The second wiring unit includes: a first connection line L1 and a second connection line L2. The first connection line L1 is connected to a plurality of second power terminals VDD. The two connecting lines L2 are connected to a plurality of second ground terminals VSS.

In this embodiment, pad1 and pad2 are used to energize several edge circuit units connected in parallel.

The edge monitoring circuit is composed of several open circuit units and second wiring units. The circuit structure is simple and the utilization rate is high.

FIG. 14 is a schematic flowchart of the working method of the edge monitoring circuit in the embodiment of the present invention.

Please refer to Figure 14, the working method of the edge monitoring circuit includes:

Step S10: Provide an edge monitoring circuit, which includes: a number of connected edge circuit units;

Step S20: After powering on the edge monitoring circuit, determine whether the edge monitoring circuit is in a short circuit or open circuit state;

Step S30: Determine whether the edge monitoring circuit is normal according to the state of the edge monitoring circuit. If the edge monitoring circuit is abnormal, perform maintenance on the edge monitoring circuit.

In one embodiment, the edge circuit unit includes a short circuit unit; according to the state of the edge monitoring circuit, the method for determining whether the edge monitoring circuit is normal includes: if the edge monitoring circuit is in a short circuit state, the edge monitoring circuit Normal; if the edge monitoring circuit is in an open circuit state, the edge monitoring circuit is abnormal and the edge monitoring circuit needs to be repaired. If the edge monitoring circuit is normal, use the edge monitoring circuit.

In another embodiment, the edge circuit unit includes an open circuit unit; according to the state of the edge monitoring circuit, the method for determining whether the edge monitoring circuit is normal includes: if the edge monitoring circuit is in an open circuit state, the edge monitoring circuit The circuit is normal; if the edge monitoring circuit is in a short-circuit state, the edge monitoring circuit is abnormal and the edge monitoring circuit needs to be repaired. If the edge monitoring circuit is normal, use the edge monitoring circuit.

By monitoring the structure of the chip edge, defects in the manufacturing process can be reduced, the yield rate can be effectively improved, and the utilization rate of the chip edge area can be improved, the cost of the wafer factory can be reduced, the redundant area of the chip can be reduced, and the product competitiveness can be improved.

FIG. 15 is a schematic flowchart of a semiconductor layout design method in an embodiment of the present invention.

Please refer to Figure 15. The semiconductor layout design method includes:

Step S100: Provide a layout, the layout including a middle area and an edge area located around the middle area;

Step S200: Provide an edge circuit unit;

Step S300: Set several connected edge circuit units in the edge area.

In one embodiment, the edge circuit unit includes a short-circuit unit; several short-circuit units are connected in series.

Several short-circuit units are connected through the first wiring unit. For structural descriptions of the short-circuit unit and the first wiring unit, please refer to FIGS. 1 to 4 and will not be described again here.

In another embodiment, the edge circuit unit includes an open-circuit unit; the open-circuit units are connected in a parallel manner.

Several open circuit units are connected through the second wiring unit. For a structural description of the open circuit unit and the second wiring unit, please refer to Figures 5 to 7 and will not be described again here.

The layout edge area design is composed of edge circuit units and wiring units, and the layout design is simple.

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims (34)

1. A semiconductor structure, comprising:

a substrate comprising a middle region and an edge region located around the middle region;

a plurality of layers of vertically stacked first and second metal layers located on the intermediate region, the first metal layer being parallel to a first direction, the second metal layer being parallel to a second direction, the first and second directions being parallel to a surface of the substrate, and the first and second directions being mutually perpendicular;

The edge circuit unit comprises a short circuit unit or an open circuit unit, the edge circuit unit comprises at least one layer of metal structure, the metal structure is parallel to the first metal layer, and the top surface of the metal structure is flush with the top surface of the first metal layer.

2. The semiconductor structure of claim 1, wherein a plurality of said edge circuit cells are located on edge regions on both sides of said intermediate region along a first direction, and wherein a plurality of said edge circuit cells are arranged along a second direction on edge regions.

3. The semiconductor structure of claim 2, wherein the edge circuit cell comprises a shorting cell; the metal structure comprises: the first input end, the first output end, the first power end, the first grounding end and a plurality of third metal layers; the short circuit unit further includes: a first plug on the third metal layer, on the first input end or on the first output end, a first connection layer on the first plug, the first connection layer being perpendicular to the third metal layer; the first connecting layer is electrically connected with the first input end, the first output end and the third metal layers, and a circuit between the first input end and the first output end is a short circuit.

4. The semiconductor structure of claim 3, wherein the plurality of shorting cells are connected in a manner such that: in the series connection mode, the first input end of the former short circuit unit is connected with the first output end of the latter short circuit unit.

5. The semiconductor structure of claim 4, wherein the first input terminal of the previous shorting unit is connected to the first output terminal of the next shorting unit through a first wiring unit comprising: the first wiring layer is connected with the first input end, the second wiring layer is connected with the first output end, the third wiring layer is electrically connected with the first wiring layer and the second wiring layer, the first wiring layer and the second wiring layer are parallel to the first metal layer, and the third wiring layer is parallel to the first connecting layer.

6. The semiconductor structure of claim 5, wherein the first wiring unit further comprises: the fourth power end is connected with the first power end, and the fourth grounding end is connected with the first grounding end, and the fourth power end and the fourth grounding end are parallel to the first metal layer.

7. The semiconductor structure of claim 3, further comprising: a fifth power terminal and a fifth ground terminal on the middle region, the fifth power terminal and the fifth ground terminal being parallel to the first direction; the first power end is connected with a fifth power end of the middle area through a first wiring unit, and the first grounding end is connected with a fifth grounding end of the middle area through the first wiring unit.

8. The semiconductor structure of claim 2, wherein the edge circuit cell comprises an open cell; the metal structure comprises: the second power end, the second grounding end and a plurality of fourth metal layers and fifth metal layers which are alternately arranged; the open circuit unit further includes: the second plug is positioned on the fourth metal layer and the second power end, the third plug is positioned on the fifth metal layer and the second grounding end, the second connecting layer is positioned on the second plug, the third connecting layer is positioned on the third plug, the fourth metal layer is vertical to the second connecting layer, and the fifth metal layer is vertical to the third connecting layer; the second connecting layer is electrically connected with the fourth metal layer and the second power supply end, the third connecting layer is electrically connected with the fifth metal layer and the second grounding end, and a circuit between the second grounding end and the second power supply end is an open circuit.

9. The semiconductor structure of claim 8, wherein the plurality of open cells are connected in a manner such that: in a parallel mode, the second power ends of the open-circuit units are connected, and the second grounding ends of the open-circuit units are connected.

10. The semiconductor structure of claim 9, wherein a plurality of open cells are connected by a second wiring cell, the second wiring cell comprising: the fourth wiring layer is connected with the second power end, the fifth wiring layer is connected with the second grounding end, the sixth wiring layer is electrically connected with the fourth wiring layers, the seventh wiring layer is electrically connected with the fifth wiring layers, the fourth wiring layer and the fifth wiring layer are parallel to the first metal layer, and the sixth wiring layer and the seventh wiring layer are parallel to the second connecting layer.

11. The semiconductor structure of claim 8, further comprising: a fifth power terminal and a fifth ground terminal on the middle region, the fifth power terminal and the fifth ground terminal being parallel to the first direction; the second power end is connected with a fifth power end of the middle area through a second wiring unit, and the second grounding end is connected with a fifth grounding end of the middle area through the second wiring unit.

12. The semiconductor structure of claim 1, further comprising: a plurality of filling units for filling voids of an edge region, the filling units comprising: the third power end and the third grounding end are parallel to the first metal layer, the third power end is connected with the first power end, and the third grounding end is connected with the first grounding end.

13. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a middle region and an edge region positioned around the middle region;

forming a plurality of vertically stacked first metal layers and second metal layers on the intermediate region, wherein the first metal layers are parallel to a first direction, the second metal layers are parallel to a second direction, the first direction and the second direction are parallel to the surface of the substrate, and the first direction and the second direction are mutually perpendicular;

And forming a plurality of connected edge circuit units on the edge area, wherein the edge circuit units comprise short circuit units or open circuit units, the edge circuit units comprise at least one layer of metal structure, the metal structure is parallel to the first metal layer, and the metal structure is flush with the top surface of the first metal layer.

14. The method of forming a semiconductor structure of claim 13, wherein the metal structure is formed simultaneously with the first metal layer; the edge circuit units are positioned on the edge areas on two sides of the middle area along the first direction, and the edge circuit units are arranged on the edge areas along the second direction.

15. The method of forming a semiconductor structure of claim 14, wherein the edge circuit cell comprises a shorting cell; the metal structure comprises: the first input end, the first output end, the first power end, the first grounding end and a plurality of third metal layers; the short circuit unit further includes: a first plug on the third metal layer, on the first input end or on the first output end, a first connection layer on the first plug, the first connection layer being perpendicular to the third metal layer; the first connecting layer is electrically connected with the first input end, the first output end and the third metal layers, and a circuit between the first input end and the first output end is a short circuit.

16. The method of forming a semiconductor structure as claimed in claim 15, wherein the plurality of shorting cells are connected in a manner such that: in the series connection mode, the first input end of the former short circuit unit is connected with the first output end of the latter short circuit unit.

17. The method of forming a semiconductor structure of claim 16, wherein the first input terminal of the preceding shorting cell is connected to the first output terminal of the following shorting cell through a first wiring cell comprising: the first wiring layer is connected with the first input end, the second wiring layer is connected with the first output end, the third wiring layer is electrically connected with the first wiring layer and the second wiring layer, the first wiring layer and the second wiring layer are parallel to the first metal layer, and the third wiring layer is parallel to the first connecting layer.

18. The method of forming a semiconductor structure of claim 15, wherein the first connection layer is formed simultaneously with the second metal layer.

19. The method of forming a semiconductor structure of claim 15, wherein the edge circuit cell comprises an open cell; the metal structure comprises: the second power end, the second grounding end and a plurality of fourth metal layers and fifth metal layers which are alternately arranged; the open circuit unit further includes: the second plug is positioned on the fourth metal layer and the second power end, the third plug is positioned on the fifth metal layer and the second grounding end, the second connecting layer is positioned on the second plug, the third connecting layer is positioned on the third plug, the fourth metal layer is vertical to the second connecting layer, and the fifth metal layer is vertical to the third connecting layer; the second connecting layer is electrically connected with the fourth metal layer and the second power supply end, the third connecting layer is electrically connected with the fifth metal layer and the second grounding end, and a circuit between the second grounding end and the second power supply end is an open circuit.

20. The method of forming a semiconductor structure as claimed in claim 19, wherein the plurality of open cells are connected in a manner such that: in a parallel mode, the second power ends of the open-circuit units are connected, and the second grounding ends of the open-circuit units are connected.

21. The method of forming a semiconductor structure of claim 20, wherein a plurality of open cells are connected by a second wiring cell, the second wiring cell comprising: the fourth wiring layer is connected with the second power end, the fifth wiring layer is connected with the second grounding end, the sixth wiring layer is electrically connected with the fourth wiring layers, the seventh wiring layer is electrically connected with the fifth wiring layers, the fourth wiring layer and the fifth wiring layer are parallel to the first metal layer, and the sixth wiring layer and the seventh wiring layer are parallel to the second connecting layer.

22. The method of forming a semiconductor structure of claim 19, wherein the second connection layer and the third connection layer are formed simultaneously with the second metal layer.

23. The method of forming a semiconductor structure of claim 13, further comprising: forming a plurality of filling units for filling voids in the edge region, the filling units comprising: the third power supply end and the third grounding end are parallel to the first metal layer.

24. An edge monitoring circuit, comprising:

a plurality of connected edge circuit units.

25. The edge monitoring circuit of claim 24 wherein the edge circuit unit comprises a shorting unit; the mode that a plurality of short-circuit units are connected is the series connection mode.

26. The edge monitoring circuit of claim 25 wherein the shorting unit comprises a first input terminal and a first output terminal, the circuit between the first input terminal and the first output terminal being a shorting circuit; the first input end of the former short-circuit unit is connected with the first output end of the latter short-circuit unit.

27. The edge monitoring circuit of claim 25 wherein the edge circuit cells comprise open circuit cells; the open circuit units are connected in parallel.

28. The edge monitoring circuit of claim 27, wherein the open circuit unit comprises: the circuit between the second grounding end and the second power end is an open circuit; the second power ends of the open-circuit units are connected, and the second grounding ends of the open-circuit units are connected.

29. A method of operating an edge monitoring circuit, comprising:

Providing an edge monitoring circuit, the edge monitoring circuit comprising: a plurality of connected edge circuit units;

after the edge monitoring circuit is electrified, judging whether the edge monitoring circuit is in a short circuit or open circuit state;

judging whether the edge monitoring circuit is normal or not according to the state of the edge monitoring circuit, and overhauling the edge monitoring circuit if the edge monitoring circuit is abnormal.

30. The method of operation of an edge monitoring circuit of claim 29, wherein the edge circuit unit comprises a shorting unit; the method for judging whether the edge monitoring circuit is normal or not according to the state of the edge monitoring circuit comprises the following steps: if the edge monitoring circuit is in a short circuit state, the edge monitoring circuit is normal; if the edge monitoring circuit is in an open circuit state, the edge monitoring circuit is abnormal and maintenance of the edge monitoring circuit is required.

31. The method of operation of an edge monitoring circuit of claim 29, wherein the edge circuit cells comprise open cells; the method for judging whether the edge monitoring circuit is normal or not according to the state of the edge monitoring circuit comprises the following steps: if the edge monitoring circuit is in an open circuit state, the edge monitoring circuit is normal; if the edge monitoring circuit is in a short circuit state, the edge monitoring circuit is abnormal and maintenance of the edge monitoring circuit is needed.

32. A semiconductor layout design method, comprising:

the layout comprises a middle area and edge areas positioned around the middle area;

providing an edge circuit unit;

and a plurality of connected edge circuit units are arranged in the edge area.

33. A semiconductor layout design method according to claim 32, wherein the edge circuit cells comprise short circuit cells; the mode that a plurality of short-circuit units are connected is the series connection mode.

34. A semiconductor layout design method according to claim 32, wherein the edge circuit cells comprise open circuit cells; the open circuit units are connected in parallel.