JP2002313938A - Semiconductor chip and semiconductor manufacturing process inspection method - Google Patents

Abstract

(57) [Summary] (with correction) [PROBLEMS] To detect a defect generated in a semiconductor device during a wiring process by a structure of the semiconductor device itself. A wiring layer of a semiconductor chip includes, in a region covering a region where a memory cell is formed, test wiring patterns not connected to any cell. This semiconductor chip has an integrated circuit layer 10 including a macro cell, a multilayer wiring layer 11 laminated on the integrated circuit layer 10, and a protective film 19 laminated on the multilayer wiring layer 11, and a processor, an SRAM, RO
M, a clock unit, and a DRAM 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device on which a test wiring pattern for evaluating a wiring process is mounted.

[0002]

2. Description of the Related Art In order to prevent troubles after integration, a TEG (Test Element) is required when a semiconductor device is developed.
Group) may be performed. The TEG is a group of evaluation single elements in which components of a semiconductor device and the like are separated and independent for evaluation, and is sometimes called a test structure or a short loop monitor.

[0003] The purpose of the reliability test by TEG is various, such as evaluation of manufacturing process and evaluation of manufacturing variation. In each reliability test, a TEG having a shape suitable for the purpose is used. For example, in a reliability test for evaluating a wiring process, a pair of comb-shaped patterns for detecting a short circuit and a meandering pattern for detecting a disconnection are used. For details of these two types of patterns, see "Integrated Circuit Manufacturability, IEEE PRE
SS, P26-P29 ".

[0004]

However, it is necessary to increase the area of the TEG, which is not a semiconductor product itself, in order to detect a random defect in the wiring process such as disconnection or short circuit. This causes an increase in the manufacturing cost of the semiconductor product.

Accordingly, an object of the present invention is to provide a semiconductor device capable of detecting a defect generated during a wiring process.

[0006]

In order to solve the above problems, according to one embodiment of the present invention, a test wiring pattern not connected to any cell is provided in a region of a wiring layer of a semiconductor chip covering a memory cell. Is included.

[0007]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

First, the structure of the semiconductor chip according to the present embodiment will be described. Here, the semiconductor chip is a device that can be a final product or a component part of the final product itself, and is different from an evaluation unit element used only for reliability evaluation.

As shown in FIG. 1 and FIG. 2, which is a sectional view taken along the line AA of FIG. 1, a semiconductor chip according to the present embodiment is an integrated circuit including a plurality of functionally integrated blocks (hereinafter, referred to as macro cells). It has a layer 10, a multilayer wiring layer 11 laminated on the integrated circuit layer 10, and a protective film 19 laminated on the multilayer wiring layer 11. Here, the integrated circuit layer 10
On the diffusion layer 10a, as the macro cell, the processor unit 1
2, SRAM unit 13, ROM unit 14, clock unit 15,
It has a DRAM section 16. The multilayer wiring layer 11 includes a plurality of wiring layers including a circuit wiring (hereinafter, random logic wiring) 18 connecting these macro cells, and an interlayer insulating film interposed between the wiring layers.

In general, the arrangement density of random logic wiring patterns varies in the multilayer wiring layers of a logic product. In a logic product in which a large-scale DRAM section 16 is mounted as a macro cell, the multilayer wiring layer 11 is usually used.
Among them, a region 11a having a small random logic wiring pattern density is located at a position covering the DRAM unit 16. Therefore, in the present embodiment, one or more test wiring patterns 17 for detecting a defect generated in the wiring process are formed in the area 11a. In the present embodiment, a wiring pattern meandering in a wiring layer (hereinafter, referred to as a meandering wiring pattern) is used as the test wiring pattern 17.
17a and a pair of comb-tooth-shaped patterns (hereinafter referred to as comb-tooth-shaped wiring patterns) 17b in which the tooth portions are inserted into each other,
Each is formed by a plurality. The former 17a is a wiring pattern for detecting disconnection (including high resistance) of the random logic wiring in the wiring layer, and the latter 17b is a wiring pattern for detecting a short circuit between random logic wirings in the wiring layer. It is. Here, the meandering wiring pattern 17a includes not only a wiring pattern meandering in one wiring layer but also a chain wiring pattern 17a 'meandering between two upper and lower wiring layers as shown in FIG. It is desirable to be able to detect a connection failure between the random logic wirings in the upper and lower wiring layers. In FIG. 3,
In order to be able to identify that the chained wiring pattern 17a 'straddles the upper and lower wiring layers, the chained wiring pattern 17a'
In a ′, the portion included in the upper wiring layer is outlined, and the portion included in the lower wiring layer is shaded.

As described above, if the test wiring pattern 17 is formed in a region having a small random logic wiring pattern density in the multilayer wiring layer of the semiconductor chip, a large number of TEGs which do not become products are separately provided from the semiconductor chip. There is no need to form them on a wafer. Therefore, the manufacturing cost can be reduced by an amount corresponding to the TEG. In addition, since the difference in wiring density between the multilayer wiring layers is suppressed, erosion due to CMP (Chemical Mechanical Polishing) or the like can be prevented. Therefore, each wiring layer of the multilayer wiring layer can be made flatter. In addition, if the test wiring patterns 17 are mixedly mounted on the individual semiconductor chips, the wiring status of all the semiconductor chips can be monitored at any time, so that an abnormality in the wiring process can be surely found.

In the above description, the test wiring pattern is formed in a portion of the multi-layer wiring layer of the semiconductor chip which covers the DRAM portion. However, the test wiring pattern must always be formed there. Not in translation. For example, a part of the wiring pattern included in the power supply wiring layer or the shield wiring layer provided on the uppermost layer of the multilayer wiring layer may be used as the test wiring pattern. Hereinafter, the structure of such a semiconductor chip will be described.

As shown in FIG. 4 and FIG. 5, which is a partially enlarged view of the AA section, a semiconductor chip in this case has a plurality of macrocells (here, processor section 22, ROM section 24) on diffusion layer 20a. , A clock unit 25 and a DRAM unit 26), a multilayer wiring layer 21 laminated on the integrated circuit layer 20, and a protective film 29 laminated on the multilayer wiring layer 21. . The multilayer wiring layer 21 includes, in order from the integrated circuit layer side, one or more (here, a plurality of) intermediate wiring layers 21a including random logic wirings 28 connecting the macro cells, and a power supply for supplying power to each macro cell. A power supply wiring layer 21b including a power supply wiring pattern 27 is included. Here, the power supply wiring pattern 27 included in the power supply wiring layer 21b partially corresponds to the meandering wiring pattern 2 used as a test wiring pattern.
7b and a comb-shaped wiring pattern 27a. Power is supplied to each macro cell via the meandering wiring pattern 27b or the comb wiring pattern 27a.

As described above, if the shape of a part of the existing power supply wiring pattern in the multilayer wiring layer of the semiconductor chip is changed to a shape that can be used as a test wiring pattern, as in the case described above, a large number of products are not obtained. Need not be formed on a wafer separately from the semiconductor chip. Further, if the meandering wiring pattern and the comb-shaped wiring pattern appear regularly on the power supply wiring pattern so as to suppress the difference in the wiring density within the power supply wiring layer, the erosion by CMP may be performed as in the case described above. Can be prevented from occurring.

Also, when the uppermost wiring layer of the multilayer wiring layer is a shield wiring layer, the shield wiring pattern included in the shield wiring layer is partially replaced with a shape (meandering) that can be used as a test wiring pattern. (Comb shape), the same effect as in the case of the power supply wiring pattern can be obtained. In this case, one end of the meandering wiring pattern or the like which is a part of the shield wiring pattern is grounded.

In each of the embodiments described above,
Although two types of wiring patterns, that is, a meandering wiring pattern and a comb-shaped wiring pattern, are formed as test wiring patterns, this is not always necessary. For example, if necessary, only one of the meandering wiring pattern and the comb wiring pattern may be formed as the test wiring pattern.

Alternatively, a wiring pattern having a shape other than the meandering wiring pattern may be formed as a test wiring pattern. For example, as shown in FIG. 6, when a random logic wiring pattern 68 is provided on a DA (design automation) grid 60 running in a predetermined direction,
A plurality of linear test wiring patterns 67 may be arranged at appropriate intervals on the DA lattice 60 between the DA lattices 60 on which the random logic wiring patterns 68 are arranged. In this case, the wiring layout is determined based on the evaluation results of the circuit simulation and the like and the layout rules determined based on the empirical rules.
Is desirably designed so as not to cause a signal delay due to the addition of.

Next, a method of inspecting a semiconductor chip having any of the above structures will be described.

The inspection for evaluating the wiring process of the semiconductor chip according to the present embodiment includes (1) measurement of the electric resistance of the test wiring pattern using a stylus, and (2) inspection of the test wiring pattern during current supply. Irradiation of light, detection of current fluctuations caused by the irradiation, (3) Detection of secondary electrons emitted from the surface by irradiating the test wiring pattern with a charged particle beam, (4)
Whether the data obtained as a result of detecting the current flowing through the test wiring pattern due to the irradiation of the charged particles, (5) measuring the surface shape of the test wiring pattern by irradiating the light or the charged particle beam, and the like is normal. It can be done by judging. For example, the inspection using the test wiring pattern 67 shown in FIG.
By irradiating the surface with charged particles, and detecting secondary electrons emitted from the surface as image signals with an electron microscope or the like. That is, the test wiring pattern 67
By detecting a contrast image corresponding to the surface potential state. If there is a short-circuited portion, the charged state is different from that of the other region only at that portion. Therefore, on the image of the electron microscope, as shown in FIG. Are different.
For this reason, the position of the short-circuit point can be specified.

Based on the results of the inspection, the cause of the wiring defect (disconnection, short circuit) occurring during the wiring process is specified, and the feedback is provided to remove the cause of the wiring defect from the wiring process. Can be. Thereby, the manufacturing process of the semiconductor chip is improved, and as a result, the yield can be improved.

[0021]

According to the present invention, a defect generated during a wiring process can be detected by the structure of the semiconductor device itself.

[Brief description of the drawings]

FIG. 1 is a cutaway view of a semiconductor chip according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a diagram showing a three-dimensional shape of a chain wiring pattern included in the semiconductor chip according to one embodiment of the present invention;

FIG. 4 is a cutaway view of the semiconductor chip according to one embodiment of the present invention.

FIG. 5 is a partially enlarged view of an AA cross section in FIG. 4;

FIG. 6 is a wiring layout diagram of a wiring layer of the semiconductor chip according to one embodiment of the present invention;

[Explanation of symbols]

 10, 20, integrated circuit layer 11, 21, multilayer wiring layer 12, 22, processor unit 13, SRAM unit 14, 24, ROM unit 15, 25, clock unit 16, 26, DRAM unit 17, 27, test wiring Patterns 17a, 27a: comb-shaped wiring patterns 17b, 27b: meandering wiring patterns

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/04 G01R 31/28 V 5F083 27/10 461 (72) Inventor Seiji Ishikawa Totsuka-ku, Yokohama-shi, Kanagawa 292 Yoshida-cho, Hitachi, Ltd. Production Technology Research Laboratory (72) Inventor Masataka Shiba 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Ltd. Hitachi, Ltd. Production Technology Research Laboratory F-term (reference) 2G014 AA01 AB59 2G132 AA15 AD15 AK07 AL12 4M106 AA02 AA11 BA02 BA14 CA16 5F033 UU05 VV12 VV16 XX37 5F038 CD12 CD20 DF05 5F083 GA09 LA17 PR40 ZA12 ZA13 ZA19 ZA20

Claims (4)

[Claims] 1. A cell group including a memory cell, and a wiring layer including a circuit wiring pattern connected to the cells of the cell group, wherein the wiring layer has a region covering a region where the memory cell is formed. A semiconductor chip including a test wiring pattern not connected to any of the cells in the cell group. 2. The semiconductor chip according to claim 1, wherein the test wiring pattern includes a pair of comb-shaped wiring patterns and / or a meandering wiring pattern inserted into each other. A semiconductor chip characterized by the above-mentioned. 3. A semiconductor chip having a plurality of cells, comprising: a multi-layer wiring layer including a wiring connected to the cell, wherein a wiring layer farthest from the cell among wiring layers included in the multi-layer wiring layer. A semiconductor chip, wherein the layer includes a pair of comb-shaped wirings and / or meandering wirings inserted into each other as a test wiring pattern. 4. The inspection method for inspecting a semiconductor chip according to claim 1, wherein an electric resistance of the test wiring pattern and a current flowing through the test wiring pattern. Change, and any of secondary electrons generated in the test wiring pattern during charged particle beam irradiation, and detecting a defect of the semiconductor chip based on the detection result. Inspection method.