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EP1380913B1 - Linearer Spannungsregler - Google Patents

Linearer Spannungsregler Download PDF

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Publication number
EP1380913B1
EP1380913B1 EP03300056.3A EP03300056A EP1380913B1 EP 1380913 B1 EP1380913 B1 EP 1380913B1 EP 03300056 A EP03300056 A EP 03300056A EP 1380913 B1 EP1380913 B1 EP 1380913B1
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EP
European Patent Office
Prior art keywords
output
input
voltage
transistor
circuit
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Expired - Lifetime
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EP03300056.3A
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English (en)
French (fr)
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EP1380913A1 (de
Inventor
Alexandre Pons
Christophe Bernard
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STMicroelectronics SA
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STMicroelectronics SA
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Publication of EP1380913A1 publication Critical patent/EP1380913A1/de
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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/247—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the supply voltage
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the present invention generally relates to the regulation of a voltage across a load. More particularly, the present invention relates to such regulation carried out linearly.
  • the document EP1061428 describes a linear regulator.
  • the figure 1 illustrates, schematically and partially, a conventional example of a linear regulator of a voltage Vout across a load (LD) 1.
  • the regulator comprises a P-channel MOS transistor 2 whose source is connected to a rail of high voltage supply Vdd and whose drain constitutes the output terminal OUT of the regulator.
  • the load 1 is connected between the OUT terminal and a low supply rail or a reference voltage or ground GND.
  • the transistor 2 operates in linear mode, that is to say that its transconductance is used to vary its output current as a function of the control voltage applied to its gate G.
  • the control voltage of the gate G is regulated according to the voltage Vout across the load 1.
  • the regulation is performed by a differential comparator 3 having an input / output stage 4 and an output stage 5.
  • the input / output stage 4 comprises two differential branches each comprising a P-channel MOS transistor 61, 62 connected in series with an N-channel MOS transistor 63, 64.
  • the sources of the transistors 61 and 62 are connected to an output terminal of a current source 60 having an input terminal connected to the high power supply Vdd.
  • the sources of transistors 63 and 64 are connected to the low GND supply.
  • the gates of transistors 63 and 64 are interconnected.
  • One branch 61-63 constitutes an input branch, while the other branch 62-64 constitutes an output branch.
  • the transistor 61 of the input branch receives a constant DC voltage setpoint Vreg supplied by a voltage generator 8 connected between the gate of the transistor 61 and the ground GND.
  • the gate of the transistor 63 is connected to its drain, that is to say also to the drain of the transistor 61.
  • the gate of the transistor 63 receives the voltage Vout across the load 1 by a connection to the output terminal OUT of regulator, possibly at an intermediate point of a resistance bridge.
  • the connection point 65 of the drains of the transistors 62 and 64 constitutes the output of the input / output stage 4 of the comparator 3.
  • the output stage 5 consists of the series connection, between the high Vdd and low GND supplies, of a generally resistive impedance (R) and of an N-channel MOS transistor 10.
  • the connection point of the impedance 9 and transistor 10 constitutes the output terminal of the differential comparator 3 connected to the gate G of the regulation transistor 2.
  • the gate of the transistor 10 is connected to the point 65 of the differential input / output branch 62-64.
  • the regulator further comprises an impedance (C) 11, generally capacitive, for stabilizing the output voltage Vout.
  • C impedance
  • the Figures 2A-2C illustrate, by timing diagrams, an example of variation as a function of the time t of the voltage setpoint Vreg at the terminals of the source 8, the output voltage Vout across the load 1, and the voltage Vds between the terminals of drain and source of the transistor 2.
  • the constant constant voltage generator 8 is enabled so that it delivers a stable non-zero nominal regulation setpoint Vref up to a time t1 circuit extinction.
  • the differential comparator 3 then forces, as illustrated by Figure 2B , the output voltage Vout to follow the regulation voltage Vreg and to align with the reference level Vref.
  • the voltage Vout is then stably regulated at the Vref level by the gate control until the instant t1 of switching off or putting the circuit on standby.
  • This regulation is performed by a linear control of transistor 2 which is used as a variable transconductance whose output current depends on the control voltage on gate G.
  • the load 1 is to be supplied at a voltage level of the order of 3.3 to 5.5 volts are more particularly considered in the present description. Such a value is relatively high compared to the maximum voltage of the order of 2.4 to 2.8 volts that can hold the components (in particular the MOS transistor 2) used in standard integration technology channels. However, during the periods of extinction of the load 1, the MOS transistor 2 must hold the voltage Vdd at its terminals.
  • the standard 2.5-volt manufacturing die has been modified to insert MOS transistors capable of holding a maximum voltage greater than 5 volts between their drain and their source.
  • MOS transistors capable of holding a maximum voltage greater than 5 volts between their drain and their source.
  • the definition masks of the regulation transistor 2 with respect to to neighboring transistors so as to substantially increase the thickness of a portion of a gate insulator near one of the drain / source regions and to increase the area of the same drain / source region.
  • the parasitic gate capacitance of transistor 2 is increased, and its transconductance is reduced.
  • it is necessary that the transconductance is relatively high. To increase it, it is then necessary to further increase the integration surface of the transistor 2.
  • bipolar type regulating transistor which has the advantage of requiring a smaller integration area relative to the specific MOS, in particular because it can more easily be integrated in a vertical in a silicon substrate.
  • the use of a bipolar transistor poses many problems.
  • CMOS sector which is more complex than the MOS sector. It is also necessary to provide a specific circuit for setting the operating point of the bipolar transistor, and in particular to provide a limitation of the base current.
  • a bipolar control transistor leads to higher waste voltages than a MOS transistor with a smaller linearity range. This is particularly disadvantageous in the case of portable type devices for which it is desirable to minimize the waste voltage, i.e. to make it, preferably, less than 200 mV.
  • the present invention aims to provide a linear regulator that overcomes the disadvantages of known circuits.
  • the present invention aims in particular to provide a linear regulator which has a reduced waste voltage.
  • the present invention aims to provide such a regulator that can be manufactured using a standard MOS die.
  • the present invention provides a linear regulator having an output stage comprising first and second P-channel MOS transistors connected in series between a first DC power terminal and an output terminal providing an output terminal. regulated output voltage, and a control circuit of the first and second transistors capable of providing first and second control signals as a function of the output voltage and the voltage at the midpoint of the series connection.
  • the control circuit comprises an input / output circuit and a reference circuit, the input / output circuit having a first input, receiving a first voltage setpoint provided by said reference circuit; a second input, connected to said output terminal; a third input receiving a second voltage setpoint supplied by said reference circuit; a fourth input connected to said midpoint; a first output connected to the gate of the first transistor; and a second output connected to the gate of the second transistor.
  • the input / output circuit is a dual differential comparator with four inputs and two outputs.
  • the input / output circuit comprises first and second differential comparators with two inputs and two outputs, the input terminals of the first differential comparator being the first and second input terminals of the input comparator. an input / output circuit and its output being the second output of said input / output circuit; and the input terminals of the second differential comparator being the third and fourth input terminals of said input / output circuit and its output being the first output.
  • the first differential comparator comprises an input / output stage and an output stage, said input / output stage comprising two differential branches, each of which comprises a P-channel MOS transistor connected in parallel. series with a first N-channel MOS transistor, the sources of the P-channel transistors being interconnected to an output terminal of a current source whose input terminal is connected to said DC power terminal, the sources of the first N-channel transistors being interconnected to a ground terminal, the gates of said first N-channel MOS transistors being interconnected, the gates of the P-channel transistors constituting the first and second input terminals of the input / output circuit, the gate of the first N-channel MOS transistor of the branch having the first input being connected to its drain, the intermediate connection point of the drains of the complementary transistors of the other branch being connected to the gate of a second N-channel MOS transistor connected in said output stage, in series between the power supply terminals, with a first impedance, the midpoint of the series connection of said first impedance and the second
  • the second differential comparator comprises two symmetrical differential branches each consisting of the series connection of a second impedance, and a third N-channel MOS transistor, respectively, the sources of the third transistors.
  • N-channel transistor being interconnected to the drain of a fourth N-channel MOS transistor having its source connected to ground, the gate of the fourth N-channel transistor being connected to the gate of the second N-channel MOS transistor of the N-channel stage; output of the first differential comparator.
  • the figure 3 represents, in the form of a block diagram, a linear regulator 30 according to an embodiment of the present invention.
  • the regulator 30 comprises an output stage 31 consisting of the series connection, between a high power supply rail Vdd and an output terminal OUT, of two P-channel MOS transistors 32 and 33.
  • the output terminal OUT is intended for to be connected to a first power supply terminal of a load (LD) 1, a second power supply terminal of which is connected to a low supply rail or ground GND.
  • the linear regulator 30 also preferably includes a stabilization impedance 11, for example a capacitor C.
  • the regulation of the voltage Vout across the terminals of the load 1, that is to say on the output terminal OUT, is effected by modulating control signals of the gates G1 and G2 of the transistors 32 and 33, respectively, so as to modify their transconductance.
  • the control signals of the output stage 31 are produced by a control circuit 35.
  • the circuit 35 modulates the control signal of the gate G1 of the transistor 32 so as to regulate the voltage at the midpoint MID of the series connection. transistors 32 and 33 of the output stage 31. It also modulates the control signal of the gate G2 of the transistor 32 so as to regulate the output voltage Vout.
  • the circuit 35 includes an input / output stage (IN / OUT) 36 for generating the control signals and a reference stage (REF) 37.
  • the input / output stage 36 comprises four input terminals I1 , I2, I3 and I4 and two output terminals O1 and O2.
  • the terminal I1 receives a regulation voltage setpoint V1 of the output voltage Vout.
  • the terminal I2 receives the output voltage Vout.
  • the terminal I3 receives a regulation voltage setpoint V2 of the voltage at the MID midpoint.
  • the terminal I4 receives the voltage Vmid of the midpoint MID by a direct connection at this point.
  • the output terminals O1 and O2 are respectively connected to the gates G1, G2.
  • FIGS. 4A, 4B, 4C and 4D respectively illustrate, by timing diagrams, the variation as a function of time t of the regulation setpoint V1 of the output voltage Vout of regulator 30 of the figure 3 , the output voltage Vout, the regulation setpoint V2 of the mid-point voltage MID and the current voltage Vmid at the midpoint MID, that is to say the drain voltage of the transistor 32.
  • the output voltage Vout follows, from time t10, the first setpoint V1 until it stabilizes at time t11 at the nominal value Vref.
  • the voltage Vmid at the midpoint MID decreases in a controlled way from half of the high power supply (Vdd / 2) to the stable value (Vdd-Vref) / 2.
  • Vdd / 2 half of the high power supply
  • Vdd-Vref stable value
  • the first setpoint V1 is progressively reduced to zero along a ramp until a time t13.
  • the supply Vdd is then distributed symmetrically on the transistors 32 and 33.
  • the control circuit 35 ensures that any fluctuation of the power at the level of the load 1 results in a variation of the setpoints V1 and V2 so as to restore the rated speed and to distribute the power variation symmetrically on the two power transistors 32 and 33.
  • the control circuit 35 ensures that neither of the two transistors 32 and / or 33 is confronted with an excessive drain / source voltage.
  • ramps of initiation and extinction of respective slope different. More particularly, there is shown a faster extinction (t12-t13) than the boot (t10-t11).
  • the slope of the ramps depends on the technical performance of the circuits and in particular the capacity of the control circuit 35 to follow, transform and transmit, the variation of the first setpoint V1. Slopes may be faster or slower than represented. In addition, they may be symmetrical or have an asymmetry inverse to that shown, that is to say that the boot can be faster than extinction.
  • the figure 5 illustrates, schematically and partially, the structure of an embodiment of the input / output stage 36 of a control circuit 35 of an output stage 31 of a regulator 30 according to the present invention.
  • the input / output circuit 36 with four inputs and two outputs is a differential comparator. More particularly, the circuit 36 consists of the combination of a first differential comparator 50 and a second differential comparator 51 interlaced in the following manner.
  • the first comparator 50 delimited by a dotted frame in figure 5 , is intended to regulate the output voltage Vout from the first setpoint V1.
  • the comparator 50 therefore has a structure similar to that of a comparator known differential such as comparator 3 described in connection with the figure 1 .
  • the structure of the comparator 50 is described below using the same references as in figure 1 .
  • the comparator 50 comprises an input / output stage 4 and an output stage 5.
  • the stage 4 comprises two differential branches each comprising a P-channel MOS transistor 61, 62 connected in series with an N-channel MOS transistor 63,
  • the sources of transistors 61 and 62 are connected to an output terminal of a current source 60 having an input terminal connected to the high power supply Vdd.
  • the sources of transistors 63 and 64 are connected to the low GND supply.
  • the gates of transistors 63 and 64 are interconnected.
  • the gate of transistor 61 constitutes terminal I1 and receives setpoint V1.
  • the gate of the transistor 63 is connected to its drain, that is to say also to the drain of the transistor 61.
  • the gate of the transistor 62 constitutes the terminal I2 and receives the current voltage Vout across the load 1 by a connection to the output terminal OUT of the controller.
  • the connection point 65 of the drains of the transistors 62 and 64 constitutes the output of the input / output stage 4 of the comparator 50.
  • the output stage 5 consists of the series connection, between the high power supply Vdd and the ground GND, of an impedance 9, preferably resistive (R), and an N-channel MOS transistor 10.
  • the point of connection of the impedance 9 and the transistor 10 constitutes the output terminal 02 providing the control signal of the gate G2 of the transistor 33.
  • the gate of the transistor 10 is connected to the midpoint 65 of the differential branch 62-64 of the entrance floor 4.
  • the second differential comparator 51 is intended to control the regulation of the voltage at the MID point. It supplies on the output terminal 01 the control signal of the gate G1.
  • the second comparator 51 comprises two symmetrical differential branches each consisting of the series connection of an impedance 52, 53, preferably resistive, and a N-channel MOS transistor 54, 55, respectively.
  • the sources of transistors 54 and 55 are connected to the drain of an N-channel MOS transistor 56 whose source is connected to ground GND.
  • the gate of the transistor 56 is connected to the output 65 of the input / output stage 4 and to the gate of the transistor 10 of the output stage 5 of the first differential comparator 50. Therefore, the operating point of the second The differential comparator 51 depends on that of the output stage 5 of the first differential comparator 50.
  • the gate G2 of the transistor 33 supplied by the first comparator 50.
  • the transistor 56 will be completely on and allow a control of the gate G1 own to limit the voltage Vmid at half (Vdd / 2) of the high feed, as has been described previously in relation to the figure 4 .
  • the gates of the transistors 54 and 55 constitute, respectively, the terminals I3 and I4 for applying the voltages V2 and Vmid.
  • the figure 6 represents, schematically and partially, an embodiment of a generator 37 of the instructions V1 and V2.
  • the reference circuit 37 is, according to an embodiment of the present invention, a resistive voltage divider.
  • the resistive divider comprises the series connection between the high supply rails Vdd and low GND of three successive resistors 71, 72 and 73.
  • the connection point 74 of the resistors 72 and 73 is the output terminal of a differential comparator 75 two inputs and one output, for example similar to the comparator 3 of the figure 1 .
  • the non-inverting input terminal of the comparator 75 receives the regulation setpoint Vreg of the output voltage Vout of the regulator 30, for example, by a connection to the source 38.
  • the inverting input terminal of the comparator 75 is connected to the output terminal 74. Thus, it copies to the terminals of the resistor 73 the first set point V1.
  • resistors 71 and 72 of the same values, the midpoint of these two resistors is controlled linearly by the comparator 75 to the desired value V2 of the half-sum of the supply voltage and the first setpoint V1.
  • the present invention advantageously provides a linear power regulator fully achievable by a low voltage standard MOS die and small dimensions. Indeed, the replacement of the high voltage MOS transistor known regulators by two low voltage transistors reduces the integration surface. In addition, the surface increase of the control portion relative to the control circuit of a known regulator is negligible compared to the surface gain associated with the change of power switch.
  • the linear regulator according to the present invention has a lower voltage drop than known regulators.
  • the high supply voltage Vdd is from 3.3 to 5.5 volts
  • each transistor 32 and 33 of the output stage 31 of the linear regulator 30 of the present invention is a transistor Standard MOS clean to hold a drain / source voltage of about 2.5 volts. The regulator's waste voltage is then reduced to values of the order of 200 mV.
  • the present invention is susceptible of various variations and modifications which will be apparent to those skilled in the art.
  • the capacitor C (impedance 11) for stabilizing the output voltage Vout has been described as being functionally part of the linear regulator 30.
  • the capacitance value of the capacitor C is relatively high and varies in depending on the application, that is to say the load 1.
  • the capacitor C is therefore preferably made outside an integrated circuit chip comprising the entire regulator 30, and is mounted directly in parallel on the load 1.
  • the skilled person will modify the characteristics of the various components to the die used.

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  • Continuous-Control Power Sources That Use Transistors (AREA)

Claims (6)

  1. Linearer Spannungsregler aufweisend eine Ausgangsstufe (31), welche erste und zweite P-Kanal-MOS-Transistoren (32, 33) umfasst, die zwischen einem ersten Gleichstromanschluss (Vdd) und einem eine geregelte Ausgangsspannung (Vout) liefernden Ausgangsanschluss (OUT) in Reihe geschaltet sind, sowie einen Schaltkreis zur Steuerung (35) der ersten und zweiten Transistoren, dadurch gekennzeichnet, dass der Steuerschaltkreis in der Lage ist, den Transistoren, in Abhängigkeit der Ausgangsspannung und der Spannung am Mittelpunkt (MID) der Reihenschaltung, erste und zweite Steuersignale zu liefern, so dass die Spannung am Mittelpunkt auf Höhe der halben Differenz zwischen dem Gleichstromanschluss und der geregelten Ausgangsspannung gehalten wird.
  2. Spannungsregler nach Anspruch 1, dadurch gekennzeichnet, dass der Steuerschaltkreis (35) einen Eingangs-/Ausgangsschaltkreis (36) und einen Referenzschaltkreis (37) umfasst, wobei der Eingangs-/Ausgangsschaltkreis Folgendes aufweist:
    einen ersten Eingang (I1), der einen vom Referenzschaltkreis ausgegebenen ersten Spannungssollwert (V1) empfängt;
    einen zweiten Eingang (I2), der mit dem Ausgangsanschluss (OUT) verbunden ist,
    einen dritten Eingang (I3), der einen vom Referenzschaltkreis ausgegebenen zweiten Spannungssollwert (V2) empfängt;
    einen vierten Eingang (I4), der mit dem Mittelpunkt (MID) verbunden ist;
    einen ersten Ausgang (O1), der mit dem Tor (G1) des ersten Transistors (32) verbunden ist; und
    einen zweiten Ausgang (O2), der mit dem Tor (G2) des zweiten Transistors (33) verbunden ist.
  3. Spannungsregler nach Anspruch 2, dadurch gekennzeichnet, dass der Eingangs-/Ausgangsschaltkreis (36) ein doppelter Differentialkomparator mit vier Eingängen und zwei Ausgängen ist.
  4. Spannungsregler nach Anspruch 2 oder 3, dadurch gekennzeichnet, dass der Eingangs-/Ausgangsschaltkreis (36) einen ersten (50) und einen zweiten (51) Differentialkomparator mit zwei Eingängen und zwei Ausgängen aufweist, wobei die Eingangsanschlüsse des ersten Differentialkomparators der erste (I1) und zweite (I2) Eingangsanschluss des Eingangs-/Ausgangsschaltkreises sind und dessen Ausgang der zweite Ausgang (O2) des Eingangs-/Ausgangsschaltkreises ist; und die Eingangsanschlüsse des zweiten Differentialkomparators der dritte (I3) und vierte (14) Eingangsanschluss des Eingangs-/Ausgangsschaltkreises sind und dessen Ausgang der erste Ausgang (O1) des Eingangs-/Ausgangschaltkreises ist.
  5. Spannungsregler nach Anspruch 4, dadurch gekennzeichnet, dass der erste Differentialkomparator (50) eine Eingangs-/Ausgangsstufe (4) und eine Ausgangsstufe (5) aufweist, wobei die Eingangs-/Ausgangsstufe zwei differentielle Zweige aufweist, die jeweils einen mit einem ersten N-Kanal-MOS-Transistor (63, 64) in Reihe geschalteten P-Kanal-MOS-Transistor (61, 62) aufweisen, wobei die Quellen der P-Kanal-Transistoren mit einem Ausgangsanschluss einer Stromquelle (60) zusammengeschaltet sind, deren einer Eingangsanschluss mit dem Gleichstromanschluss (Vdd) verbunden ist, wobei die Quellen der ersten N-Kanal-Transistoren mit einem Erdungsanschluss (GND) zusammengeschaltet sind, wobei die Tore der ersten N-Kanal-MOS-Transistoren zusammengeschaltet sind, wobei die Tore der P-Kanal-Transistoren den ersten (I1) und zweiten (I2) Eingangsanschluss des Eingangs-/Ausgangsschaltkreises (36) bilden, wobei das Tor des ersten N-Kanal-MOS-Transistors des den ersten Eingang aufweisenden Zweigs (61-63) mit dessen Senke verbunden ist, wobei der Mittelpunkt (65) der Schaltung der Senken der komplementären Transistoren des anderen Zweigs (62-64) mit dem Tor eines zweiten N-Kanal-MOS-Transistors (10) verbunden ist, der in der Ausgangsstufe (5) zwischen den Stromanschlüssen mit einer ersten Impedanz (9) in Reihe geschaltet ist, wobei der Mittelpunkt der Reihenschaltung der ersten Impedanz und des zweiten Transistors den Ausgangsanschluss (O2) des ersten Differentialkomparators bildet.
  6. Spannungsregler nach Anspruch 5, dadurch gekennzeichnet, dass der zweite Differentialkomparator (51) zwei symmetrische differentielle Zweige aufweist, die jeweils aus der Reihenschaltung einer zweiten Impedanz (52, 53) und eines dritten N-Kanal-MOS-Transistors (54, 55) bestehen, wobei die Quellen der dritten N-Kanal-MOS-Transistoren mit der Senke eines vierten N-Kanal-MOS-Transistors (56) verbunden sind, dessen Quelle mit der Masse (GND) verbunden ist, wobei das Tor des vierten N-Kanal-Transistors mit dem Tor des zweiten N-Kanal-MOS-Transistors (10) der Ausgangsstufe (5) des ersten Differentialkomparators (50) verbunden ist.
EP03300056.3A 2002-07-09 2003-07-09 Linearer Spannungsregler Expired - Lifetime EP1380913B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0208624A FR2842316A1 (fr) 2002-07-09 2002-07-09 Regulateur de tension lineaire
FR0208624 2002-07-09

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EP1380913A1 EP1380913A1 (de) 2004-01-14
EP1380913B1 true EP1380913B1 (de) 2017-11-22

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US20040008015A1 (en) 2004-01-15
FR2842316A1 (fr) 2004-01-16
US6894467B2 (en) 2005-05-17

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