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EP1093044B1 - Linearer Regler mit niedrigem seriellen Spannungsabfall - Google Patents

Linearer Regler mit niedrigem seriellen Spannungsabfall Download PDF

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Publication number
EP1093044B1
EP1093044B1 EP00410123A EP00410123A EP1093044B1 EP 1093044 B1 EP1093044 B1 EP 1093044B1 EP 00410123 A EP00410123 A EP 00410123A EP 00410123 A EP00410123 A EP 00410123A EP 1093044 B1 EP1093044 B1 EP 1093044B1
Authority
EP
European Patent Office
Prior art keywords
transistor
regulator
circuit
resistor
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP00410123A
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English (en)
French (fr)
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EP1093044A1 (de
Inventor
Nicolas Marty
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STMicroelectronics SA
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STMicroelectronics SA
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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/468—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC characterised by reference voltage circuitry, e.g. soft start, remote shutdown
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S323/00—Electricity: power supply or regulation systems
    • Y10S323/901—Starting circuits

Definitions

  • the present invention relates to the field of linear voltage regulators which are intended to supply a regulated voltage from a reference voltage and an unstabilized supply voltage.
  • the invention relates, more particularly, to regulators of which a power element is connected in series with the load to be supplied and which are designed to introduce a low series voltage drop (LDO), so as to be able to operate with a voltage of minimum supply.
  • LDO low series voltage drop
  • FIG. 1 represents a classic example of a linear regulator to which the present invention applies.
  • a regulator is intended to supply a load (Q) 2.
  • the regulator essentially consists of a power MOS transistor 1 intended to be connected in series with the load 2. This association in series is connected between a terminal 3 of application of a more positive potential Vbat and a terminal 4 of application of a more negative potential (for example, mass).
  • the voltage Vbat is, for example, supplied by a battery (not shown).
  • the transistor 1 is controlled by a regulation circuit 5, generally based on a differential amplifier.
  • a first inverting input of circuit 5 receives a reference voltage Vref and a second non-inverting input receives the output voltage Vout, taken at the midpoint of the association in series of transistor 1 with load 2. This midpoint constitutes terminal 6 of the regulator output.
  • a capacitor C is generally connected between terminal 6 and ground to filter and stabilize the output voltage Vout.
  • a regulator as illustrated in FIG. 1 is perfectly conventional and will not be detailed. We will limit our to signaling that the amplifier 5 is, most often, supplied by the voltage Vbat and that the reference voltage Vref is generally supplied by a reference circuit suitable for delivering a stable and precise voltage, for example, a circuit of the type known by the Anglo-Saxon name "bangap".
  • linear regulators An example of an application of linear regulators is the field of mobile telephones.
  • the telephone battery is used to power one or more linear regulators which must, downstream, provide the power supplies necessary for the different polarization, control and digital and analog processing circuits.
  • the voltage Vout delivered by the regulator must generally be very precise. For example, in a telephony application, an accuracy of plus or minus 3% is desired.
  • the power transistor 1 is generally bulky insofar as the regulator must operate over the entire operating range in current of the circuits which it supplies downstream.
  • the surface necessary to produce the power transistor is of the order of 1 mm 2 .
  • the importance of the surface area required is also linked to the fact that, in order to comply with the constraint of a low voltage drop in series, the resistance of transistor 1 must be, in the on state (RdsON), the lowest possible.
  • the transistor 1 When the circuit is energized or, more precisely, when the regulator is switched on by a specific signal, the transistor 1 then supplies a large current to the capacitor C which charges. As long as the voltage Vout does not reach the desired voltage Vref at the output, the amplifier 5 remains unbalanced. When the voltages Vout and Vref become equal, the output terminal of the amplifier 5 switches to stop the large current supply in the transistor 1. However, due to the high gate capacity of the transistor 1, this does not is not loaded immediately and there is a delay in the circuit reaction. The output voltage then exceeds the desired value and there is an overvoltage.
  • the output stage (not shown in FIG. 1) of the amplifier 5 generally consists of an N-channel MOS transistor (more precisely, of the type of channel opposite to that of the power transistor) in series with a source of current.
  • the current source is itself in parallel with a resistance, called a gate, whose role is, precisely, to charge the gate capacitance of the power transistor 1 when the output of the amplifier switches.
  • the gate resistor is also used to set the gain of the amplifier and conditions the stability of the circuit. Another role of this resistance is to polarize the output stage of the amplifier 5. Consequently, the value of this resistance also conditions the consumption of the circuit.
  • a gate whose role is, precisely, to charge the gate capacitance of the power transistor 1 when the output of the amplifier switches.
  • the gate resistor is also used to set the gain of the amplifier and conditions the stability of the circuit. Another role of this resistance is to polarize the output stage of the amplifier 5. Consequently, the value of this resistance also conditions the consumption of the circuit.
  • the value of this resistance also conditions the consumption
  • the present invention aims to propose a new solution which overcomes the problems of overvoltage at the start of conventional linear regulators.
  • the present invention aims, in particular, to propose a solution which is compatible with low consumption of the circuit in steady state.
  • the invention also aims to propose a solution which is easily configurable for adjusting the response time of the circuit at start-up.
  • a first solution would be to modify the voltage reference of the amplifier, during start-up.
  • this solution is undesirable in practice since the same voltage reference is generally used for several linear regulators. Consequently, by modifying this reference, there is a risk of adversely affecting the functioning of other regulators which would themselves be in steady state.
  • the present invention aims to propose a solution which is compatible with individualized operation of several regulators using the same voltage reference.
  • the present invention provides a linear regulator of the type comprising a power MOS transistor of a first type of channel, controlled by an amplifier, one output stage of which comprises, between two terminals for applying a voltage d power supply, a first resistor and a first MOS transistor for controlling a second type of channel, the regulator comprising a starting circuit having a resistor switchable in parallel on said first resistor.
  • the starting circuit comprises, in series between the source and the gate of the power MOS transistor, said switchable resistor and first and second MOS control transistors of the first type of channel.
  • the two MOS transistors for controlling the starting circuit are on when the regulator is switched on, the blocking of the first transistor being progressive by means of a control ramp.
  • the second transistor of the starting circuit is blocked at the end of the blocking ramp of the first transistor.
  • the duration of the blocking ramp of the first transistor is chosen to be significantly greater than the time necessary, at the output of the linear regulator, to reach a desired voltage.
  • the starting circuit comprises a ramp generator for controlling the first control transistor and a latching logic circuit for abruptly opening the second control transistor at the end of the control ramp for the first transistor.
  • the resistance of the starting circuit is at least ten times less than the resistance of the output stage of the control amplifier.
  • the power transistor is P-channel to constitute a positive voltage regulator.
  • the power transistor is N-channel to constitute a negative voltage regulator.
  • the invention also provides a method for controlling a linear regulator consisting of a power MOS transistor and a regulation amplifier, an output stage of which, in series between two supply terminals, a resistor and a transistor Control MOS, of opposite channel type with respect to the power transistor, the method consisting in decreasing said resistance when starting the regulator.
  • the method consists in switching a resistance in parallel with the resistance of the output stage of the amplifier.
  • a characteristic of the present invention is to provide, between the gate of the power transistor (for example, with P channel) and the terminal (opposite to the load) of application of the supply voltage to which this transistor is connected in direct, switchable resistance. According to the invention, this resistance is controlled to be inserted into the circuit only when the regulator starts, and is of value less than that of the resistance of the output stage of the regulation amplifier.
  • FIG. 2 very schematically shows a regulator 10 according to an embodiment of the present invention.
  • the regulator comprises a regulating amplifier 5, connected between a terminal 3 for applying a positive voltage Vbat and ground 4, and which is responsible for controlling a power MOS transistor 1, connected between terminal 3 and an output terminal 6 to which a load 2 is connected.
  • a linear regulator using a P-channel power MOS transistor and delivering a positive voltage. Note however that the invention also applies to the case of a negative voltage regulator or a regulator whose power MOS transistor is N channel.
  • the conventional amplifier 5 essentially consists of a differential stage 11 receiving, on an inverting terminal, the reference voltage Vref fixing the value of the desired output voltage and, on a non-inverting terminal, the output voltage Vout of the regulator taken from the drain 6 of the transistor 1. If necessary, a resistive divider bridge can be introduced, between the terminal 6 and the non-inverting input of the amplifier 5, to obtain a voltage Vout greater than the voltage Vref.
  • the differential stage 11 is supplied by a current source 12 connected to the terminal 3.
  • the output 13 of the differential stage is sent to an output stage 14 constituted, in series between the terminals 3 and 4, of a source current 15 and a MOS transistor (here, N channel) 16 whose gate is connected to terminal 13.
  • the midpoint 17 of the series association of the current source 15 and of transistor 16 constitutes the output terminal of amplifier 5, connected to the gate of transistor 1.
  • a resistor Rg, having the role of fixing the gain of amplifier 5, of ensuring its stability and to charge the gate of transistor 1, is connected in parallel on the current source 15.
  • a starting circuit 20 consisting, functionally, of a switch 21 in series with a resistor 22 is connected in parallel to the resistor Rg.
  • the value of the resistor 22 is chosen to be low (of preferably in a ratio of 10 to 100) relative to the value of the resistance Rg.
  • a resistance 22 of between 1 and 10 k ⁇ will preferably be chosen.
  • control of the starting circuit that is to say the switching of the switch 21
  • the switching of the switch 21 must meet certain constraints. In particular, care will be taken not to reproduce, on the switching of this switch, the delay in switching detrimental to the operation of conventional regulators.
  • Another characteristic of the present invention is to associate, in series with the resistor 22 of the starting circuit, two switches (preferably two MOS transistors) controlled in a particular way as we will see later.
  • FIG. 3 partially shows an embodiment of a starting circuit according to the invention, comprising a switch 21 in series with a resistor 22.
  • the switch 21 is here constituted, between terminal 3 and a first terminal resistor 22, the second terminal of which is connected to terminal 17, of a first MOS transistor MR, with P channel, in series with a second MOS transistor ML, with P channel.
  • the transistor MR is controlled by a STARTUP signal while that the transistor ML is controlled by a LOCK signal.
  • the STARTUP signal has the form of a ramp, the role of which is to control the MR transistor in linear fashion, following ignition, to increase its series resistance (RdsON) which is added to resistance 22, the ML transistor being in a normally closed rest state when the circuit is switched on.
  • the STARTUP signal is normally low so that, when the regulator starts, the MR transistor is closed with a minimum series resistance (RdsON).
  • the progressive increase in the series resistance of the transistor MR progressively increases the resistance in parallel on the resistance Rg and, consequently, causes a progressive switching when the start-up circuit of the invention opens.
  • the control ramp at the opening of the MR transistor must be slow enough for the start-up to be finished at the end of the ramp. In other words, it must be ensured that the capacitor C has reached the desired voltage level before the end of the opening ramp of the transistor MR.
  • the role of the transistor ML is to lock the opening of the starting circuit to prevent a possible disturbance of the battery voltage Vbat from again making the transistor MR pass under the effect of a parasitic conduction of the ramp generator as we will see it later.
  • the transistor ML is controlled by an edge, which is not troublesome insofar as, when one causes its opening, the starting circuit is already, in practice, opened by the transistor MR.
  • FIG. 4 represents a preferred embodiment of a starting circuit 20 according to the present invention.
  • FIG. 4 not only represents the series association of the transistors MR and ML constituting the switch 21 with the resistor 22, but also the circuit for generating the respective signals STARTUP and LOCK for controlling the transistors MR and ML.
  • the circuit 20 is based on a ramp generator 31 delivering the STARTUP signal, associated with a logic locking circuit 32 intended to generate the LOCK signal when the STARTUP signal has reached its high state.
  • FIG. 4 also shows, by way of example, stages 33, 34 delivering signals BP and BN for biasing the P-channel and N-channel MOS transistors respectively.
  • the circuit 20 of the invention is intended to be controlled exclusively by the activation signal of the linear regulator.
  • This signal consists of a logic signal PD and its inverse PDN.
  • FIG. 4 the mechanism for inverting the PD extinction or PDN ignition signal has not been shown.
  • the bias circuit 33 is, for example, constituted, in series between the terminals 3 and 4, of an MOS transistor MP1, with P channel, and of a current source 35.
  • the transistor MP1 is mounted as a diode, its source being connected to terminal 3 and its drain being connected to a first terminal of current source 35, the other terminal of which is connected to ground 4.
  • the drain of transistor MP1 is also connected to its gate and to the drain of transistor MP5, and constitutes the output terminal of the circuit 33 delivering the signal BP.
  • the current source 35 is, for example, formed of a resistor or an MOS transistor, with N channel, correctly polarized.
  • the bias circuit 34 is, for example, constituted, in series between terminal 3 and terminal 4, of a current source 36 and of an MOS transistor MN1, with N channel.
  • the transistor MN1 is mounted as a diode, its source being connected to terminal 4 and its drain being connected to a first terminal of current source 36, the other terminal of which is connected to terminal 3.
  • the drain of transistor MN1 is also connected to its gate and the gate of the transistor MN5, and constitutes the output terminal of the circuit 34 delivering the signal BN.
  • the current source 36 is, for example, formed of a resistor or an MOS transistor, with P channel, correctly polarized.
  • the signals BP and BN are, respectively, substantially at the potentials Vbat-Vtp (Vtp represents the threshold voltage d 'a P-channel MOS transistor) and Vtn (Vtn represents the threshold voltage of an N-channel MOS transistor).
  • the ramp generator 31 is based on the use, in series between terminals 3 and 4, of an MP3 MOS transistor, with P channel, associated with a capacitor C1 and, for locking, as will be seen below, of an MOS transistor MN3, with N channel.
  • the source of the transistor MP3 is connected to terminal 3. Its drain is connected to a first terminal of capacitor C1 which sets the time constant for the ramp.
  • the other terminal of capacitor C1 is connected to the drain of transistor MN3, the source of which is connected to ground.
  • the gate of the MP3 transistor is connected, via a MOS MP4 transistor, with P channel, to terminal 3.
  • the transistor MP4 is controlled by the PDN signal and its drain is, in addition, connected to the gate of the MP3 transistor , connected to the source of an MP5 MOS transistor, with P channel, the drain of which receives the signal BP and the gate of which receives the signal PD.
  • the drain of the MP3 transistor which constitutes the output terminal 37 of the ramp generator 31 is also connected, via an MOS transistor MN4, with N channel, controlled by the signal PD, to the terminal 4.
  • the role of the transistor MP4 is to force, by passing, the blocking of the MP3 transistor when the signal PDN is in the low state, that is to say when the regulator is off.
  • the role of the transistor MP5 is, conversely, to force the conduction of the transistor MP3 by being conductive when the signal PD is in the low state, that is to say when the regulator is on.
  • the role of the transistor MN4 is to short-circuit the capacitor C1 and the transistor MN3 when the signal PD is in the high state, that is to say when the regulator is switched off.
  • the STARTUP signal delivered by the output terminal 37 of the ramp generator 31, is sent directly to the gate of the transistor MR and at the input of the latching circuit 32.
  • Circuit 32 includes, in series between terminals 3 and 4, a MOS transistor MP6, with P channel, and two MOS transistors MN5 and MN6, with N channel.
  • the source of transistor MP6 is connected to terminal 3. Its gate receives the STARTUP signal. Its drain is connected to the drain of transistor MN6 whose gate receives the signal PDN.
  • the source of transistor MN6 is connected to the drain of transistor MN5 whose source is connected to terminal 4 and whose gate receives the signal BN.
  • the common drain of the transistors MP6 and MN6 is also connected to the input of an inverter 38 whose output is sent to a flip-flop 39 consisting, for example, of two gates 40 and 41, of the NOR type (NOR) .
  • the output of the inverter 38 is sent to a first input of door 40, the output of which is sent to a first input of door 41.
  • the output of door 41 constitutes the output of flip-flop 39, sent to the second input of gate 40.
  • the second input of gate 41 receives the signal PD.
  • the output of flip-flop 39 delivers the LOCK signal.
  • the output of flip-flop 39 is also preferably sent, via an inverter 42, to the gate of transistor MN3.
  • transistor MN3 The role of transistor MN3 is to avoid permanent consumption, outside start-up periods, by isolating the ramp generator when the LOCK signal goes high.
  • the role of the transistor MP6 is to open the input branch of the circuit 32 when the regulator is off and thus to eliminate the consumption in this circuit 32.
  • FIGS. 5A to 5F represent, in the form of timing diagrams, an example of the pattern of signals characteristic of a regulator according to the invention.
  • FIG. 5A represents the shape of the PDN signal.
  • FIG. 5B shows the shape of the PD signal.
  • FIG. 5C shows the shape of the STARTUP signal.
  • Figure 5D shows the shape of the LOCK signal.
  • FIG. 5E represents the shape of the gate signal V17 of the power transistor 1 of the regulator.
  • FIG. 5F represents the shape of the voltage Vout at the output of the regulator.
  • the PDN and PD signals are respectively in the low state and in the high state.
  • Point 37 is drawn to ground by transistor MN4 which is on and the STARTUP signal is therefore in the low state.
  • the MR transistor is therefore on.
  • the transistor MP6 is passed through the low state of the node 37 while the transistor MN6 is blocked by the low state of the signal PDN. This results in a high level at the input of the inverter 38 and, consequently, a low state at the output of the flip-flop 39, that is to say at the input of the inverter 42.
  • the transistor ML is therefore good on , the LOCK signal being low.
  • the transistor MN3 is also on.
  • the ramp generator 31 is therefore ready to operate.
  • the transistor MP4 is blocked by setting the PDN signal to the high state.
  • the transistor MP5 is turned on by setting the PD signal to the low state. It follows that the MP3 transistor becomes conducting, the current in the MP3 transistor being fixed by the current in the transistor MP1, therefore by the signal BP.
  • the transistor MN4 is blocked at the instant t0 by setting the signal PD to the low state, the capacitor C1 is charged by the transistor MP3.
  • the MP3 transistor As long as the MP3 transistor is saturated, it provides a constant charge current for the capacitor C1.
  • the circuit 33 and, more particularly, the sizes of the transistors MP1 and MP5, are chosen adequately so that the transistor MP3 is in saturation.
  • the charging of the capacitor C1 under constant current does indeed cause an increasing voltage ramp on the gate of the transistor MR (FIG. 5C), therefore a progressive opening of this transistor by increasing its series resistance (RdsON).
  • the output of flip-flop 39 switches. Indeed, the transistor MP6 is blocked.
  • the input of the inverter 38 switches to the low state. Its output switches to the high state and the output of the gate 40 then switches to the low state.
  • the output of door 41 switches to the high state and, by looping back onto the input of door 40, the state then obtained is stable.
  • the high state output of flip-flop 39 (LOCK signal) blocks transistor ML. This blocking of the transistor ML occurs when the transistor MR is itself already completely blocked by the ramp of the STARTUP signal.
  • the transistor MN3 is blocked by the passage to the high state of the output of the flip-flop 39, inverted by the inverter 42, so that the ramp generator 31 is disconnected.
  • flip-flop 39 The role of flip-flop 39 is in fact to memorize the state of the STARTUP signal the first time when, following the ignition of the regulator, the Vbat voltage is approached on the STARTUP signal.
  • the potential of node 37 can no longer vary once the signal LOCK has gone high, as long as the signal PD does not switch, that is to say as long as it this is not a caused re-ignition.
  • the transistor MN4 discharges the capacitor C1 of the ramp generator, in order to replace it in a correct operating position for the next ignition.
  • FIG. 5E illustrates the shape of the voltage V17 on the gate of the transistor 1. It can be seen that, at the instant t 0 , the voltage V17 drops to make the transistor 1 on. The capacitor C therefore charges under a large current and there results an increase in the voltage Vout. When the voltage Vout reaches the reference voltage Vref (instant t 2 , FIG. 5F), the amplifier 5 (FIG. 2) switches and the transistor 1 is blocked. As we are at the start of the ramp of the STARTUP signal, the resistor 22 is then fully in parallel with the resistor Rg, which considerably accelerates the blocking of the transistor 1 compared to the conventional circuit.
  • the time ⁇ required to block transistor 1 is equal to Cg * RgR22 / (Rg + R22), where R22 and Rg are the respective values of resistors 22 and Rg, and where Cg denotes the gate capacitance of transistor 1.
  • the value of the resistance 22 is chosen to be at least ten times greater than the resistance Rg of the output stage of the control amplifier, in order to minimize the time ⁇ .
  • An advantage of the present invention is that it makes it possible to avoid overvoltages at the start of a linear regulator.
  • Another advantage of the present invention is that it does not require other control signals than those usually available for controlling a regulator.
  • the only signals necessary for the operation of the starting circuit are the PD and PDN signals which are used to switch the regulator on / off.
  • Another advantage of the present invention is that it does not entail any additional consumption in the regulator in steady state.
  • the present invention is susceptible to various variants and modifications which will appear to those skilled in the art.
  • the dimensioning of the various components of the circuit of the invention can be chosen by a person skilled in the art according to the application and, in particular, according to the desired currents and the desired ramp time for the starting circuit.
  • the invention has been described above in relation to a regulator using a P-channel power MOS transistor, the adaptation of the starting circuit of the invention to a regulator using a MOS power transistor at N channel is within the reach of the skilled person from the functional indications given above. Similarly, the adaptation of the starting circuit and the regulator to deliver a negative voltage is within the reach of the skilled person.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Claims (10)

  1. Ein Linear-Regler der Bauart, der einen Leistungs-MOS-Transistor (1) eines ersten Kanaltyps (P), aufweist und zwar gesteuert durch einen Verstärker (5) mit einer Ausgangsstufe, die zwischen zwei Leistungsversorgungs-(Vbat)-Anschlüssen (3, 4), einen Widerstand (Rg) und einen ersten MOS Steuertransistor (16) eines zweiten Kanaltyps (N) im Gegensatz zum Kanaltyp des Leistungs-MOS-Transistors aufweist, dadurch gekennzeichnet, dadurch dass eine Startschaltung (20) vorgesehen ist, die einen schaltbaren Widerstand (22) parallel zu dem ersten Widerstand (Rg) aufweist.
  2. Der Regler nach Anspruch 1, wobei die Startschaltung (20) in Serie zwischen der Source und dem Gate des Leistungs-MOS-Transistors (1), den schaltbaren Widerstand (22) aufweist und erste (MR) und zweite (ML) MOS-Steuertransistoren des ersten Kanaltyps (P).
  3. Der Regler nach Anspruch 2, wobei die zwei MOS-Steuertransistoren der Startschaltung (20) beim Einschalten des Reglers eingeschaltet sind, wobei das Abschalten, des ersten Transistors (MR) progressiv durch eine Steuerrampe (STARTUP) erfolgt.
  4. Der Regler nach Anspruch 3, wobei der zweite Transistor (ML) in der Startschaltung (20) am Ende der Abschaltrampe (STARTUP) des ersten Transistors (MR) abgeschaltet wird.
  5. Der Regler nach den Ansprüchen 3 oder 4, wobei die Dauer oder Länge der Startrampe (STARTUP) des ersten Transistors (MR) derart gewählt, dass sie viel größer ist, als die Zeit die notwendig ist, um am Ausgang des linearen Reglers eine Sollspannung zu erreichen.
  6. Der Regler nach einem Ansprüche 3 bis 5, wobei die Startschaltung (20) einen Rampengenerator (31) aufweist, um den ersten Steuertransistor (MR) zu steuern und eine Verriegelungslogikschaltung (32), um den zweiten Steuertransistor (ML) abrupt am Ende der Steuerrampe (STARTUP) des ersten Transistors abzuschalten.
  7. Der Regler nach einem der Ansprüche 1 bis 6, wobei der Widerstandswert (22) der Startschaltung (20) mindestens zehnmal kleiner ist als der Widerstand (Rg) der Ausgangsstufe des Steuerverstärkers (5).
  8. Der Regler nach einem der Ansprüche 1 bis 7, wobei der Leistungstransistor (1) einen P Kanal besitzt, um einen positiven Spannungsregler zu bilden.
  9. Der Regler nach einem der Ansprüche 1 bis 7, wobei der Leistungstransistor einen N Kanal besitzt, um einen negativen Spannungsregler zu bilden.
  10. Ein Verfahren zur Regelung bzw. Steuerung eines Linearreglers gemäß nach einem der Ansprüche 1 bis 9, dadurch gekennzeichnet dass, die Verringerung des Wertes des erwähnten Widerstandes beim Starten des Reglers vorgesehen ist, und zwar in Folge der parallelen Assoziation des ersten Widerstandes (Rg) der Ausgangsstufe des Verstärkers (5) mit dem schaltbaren Widerstand (22).
EP00410123A 1999-10-13 2000-10-12 Linearer Regler mit niedrigem seriellen Spannungsabfall Expired - Lifetime EP1093044B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9912978 1999-10-13
FR9912978A FR2799849B1 (fr) 1999-10-13 1999-10-13 Regulateur lineaire a faible chute de tension serie

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EP1093044A1 EP1093044A1 (de) 2001-04-18
EP1093044B1 true EP1093044B1 (de) 2004-12-29

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US (1) US6445167B1 (de)
EP (1) EP1093044B1 (de)
DE (1) DE60017049T2 (de)
FR (1) FR2799849B1 (de)

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DE60017049T2 (de) 2006-01-12
FR2799849A1 (fr) 2001-04-20
FR2799849B1 (fr) 2002-01-04
DE60017049D1 (de) 2005-02-03
EP1093044A1 (de) 2001-04-18
US6445167B1 (en) 2002-09-03

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