EP1380913B1 - Linear voltage regulator - Google Patents

Description

The present invention generally relates to the regulation of a voltage across a load. More particularly, the present invention relates to such regulation carried out linearly. The document EP1061428 describes a linear regulator. The figure 1 illustrates, schematically and partially, a conventional example of a linear regulator of a voltage Vout across a load (LD) 1. The regulator comprises a P-channel MOS transistor 2 whose source is connected to a rail of high voltage supply Vdd and whose drain constitutes the output terminal OUT of the regulator. The load 1 is connected between the OUT terminal and a low supply rail or a reference voltage or ground GND. The transistor 2 operates in linear mode, that is to say that its transconductance is used to vary its output current as a function of the control voltage applied to its gate G. The control voltage of the gate G is regulated according to the voltage Vout across the load 1. The regulation is performed by a differential comparator 3 having an input / output stage 4 and an output stage 5. The input / output stage 4 comprises two differential branches each comprising a P-channel MOS transistor 61, 62 connected in series with an N-channel MOS transistor 63, 64. The sources of the transistors 61 and 62 are connected to an output terminal of a current source 60 having an input terminal connected to the high power supply Vdd. The sources of transistors 63 and 64 are connected to the low GND supply. The gates of transistors 63 and 64 are interconnected. One branch 61-63 constitutes an input branch, while the other branch 62-64 constitutes an output branch. The transistor 61 of the input branch receives a constant DC voltage setpoint Vreg supplied by a voltage generator 8 connected between the gate of the transistor 61 and the ground GND. The gate of the transistor 63 is connected to its drain, that is to say also to the drain of the transistor 61. The gate of the transistor 63 receives the voltage Vout across the load 1 by a connection to the output terminal OUT of regulator, possibly at an intermediate point of a resistance bridge. The connection point 65 of the drains of the transistors 62 and 64 constitutes the output of the input / output stage 4 of the comparator 3.

The output stage 5 consists of the series connection, between the high Vdd and low GND supplies, of a generally resistive impedance (R) and of an N-channel MOS transistor 10. The connection point of the impedance 9 and transistor 10 constitutes the output terminal of the differential comparator 3 connected to the gate G of the regulation transistor 2. The gate of the transistor 10 is connected to the point 65 of the differential input / output branch 62-64.

The regulator further comprises an impedance (C) 11, generally capacitive, for stabilizing the output voltage Vout.

The Figures 2A-2C illustrate, by timing diagrams, an example of variation as a function of the time t of the voltage setpoint Vreg at the terminals of the source 8, the output voltage Vout across the load 1, and the voltage Vds between the terminals of drain and source of the transistor 2. When starting the circuit, at a time t0, the constant constant voltage generator 8 is enabled so that it delivers a stable non-zero nominal regulation setpoint Vref up to a time t1 circuit extinction. The differential comparator 3 then forces, as illustrated by Figure 2B , the output voltage Vout to follow the regulation voltage Vreg and to align with the reference level Vref. The voltage Vout is then stably regulated at the Vref level by the gate control until the instant t1 of switching off or putting the circuit on standby. This regulation is performed by a linear control of transistor 2 which is used as a variable transconductance whose output current depends on the control voltage on gate G.

Applications in which the load 1 is to be supplied at a voltage level of the order of 3.3 to 5.5 volts are more particularly considered in the present description. Such a value is relatively high compared to the maximum voltage of the order of 2.4 to 2.8 volts that can hold the components (in particular the MOS transistor 2) used in standard integration technology channels. However, during the periods of extinction of the load 1, the MOS transistor 2 must hold the voltage Vdd at its terminals.

Indeed, as illustrated by Figure 2C during the phases of extinction of the charge 1 (Vreg = 0, Figure 2A ), that is to say before the start time t0 and after the extinction time t1, the load control transistor 2 must withstand, between its drain and source terminals, a difference of potential Vds equal to the supply amplitude Vdd-GND. On the other hand, during the operation of the load 1 (Vreg = Vref), the voltage Vds is reduced to the difference between the high power supply Vdd and the voltage Vout at the terminals of the load 1, that is to say the value nominal regulation Vref.

To enable the voltage resistance of the transistor 2 during the extinction phases, the standard 2.5-volt manufacturing die has been modified to insert MOS transistors capable of holding a maximum voltage greater than 5 volts between their drain and their source. In particular, the definition masks of the regulation transistor 2 with respect to to neighboring transistors, so as to substantially increase the thickness of a portion of a gate insulator near one of the drain / source regions and to increase the area of the same drain / source region. But then, the parasitic gate capacitance of transistor 2 is increased, and its transconductance is reduced. However, to allow a linear control of the transistor 2 as described above with sufficiently low control levels, it is necessary that the transconductance is relatively high. To increase it, it is then necessary to further increase the integration surface of the transistor 2.

Surface increase means that these control switches must sometimes be integrated outside the chip in which the rest of the power circuit constituting the voltage regulator is made. In addition, it is then necessary to take into account a relatively high parasitic capacitance compared to the parasitic capacitances of the other elements of the circuit. In addition, the waste voltage, that is to say the difference between the regulation setpoint Vref and the output voltage Vout can hardly be reduced to less than 500 mV. This is particularly disadvantageous in portable devices such as electronic diaries, satellite phones, laptops or handheld organizers. Indeed, to obtain the nominal output level necessary for the proper operation of the load, requires the use of a set of higher level. This increases the size of the circuit and / or, more generally, then causes an accelerated discharge of the batteries supplying the entire circuit and to provide the reference setpoint Vref. In the latter case, it is necessary to frequently recharge the batteries of the device, which is in contradiction with their wearable nature.

Moreover, the changes in the manufacturing process necessary for the formation of the regulating MOS transistor are particularly troublesome in terms of the complexity of the overall process and cost.

To overcome these problems, it has been proposed to use a high-voltage bipolar type regulating transistor, which has the advantage of requiring a smaller integration area relative to the specific MOS, in particular because it can more easily be integrated in a vertical in a silicon substrate. However, the use of a bipolar transistor poses many problems.

In particular, it is necessary to resort to a BiCMOS sector which is more complex than the MOS sector. It is also necessary to provide a specific circuit for setting the operating point of the bipolar transistor, and in particular to provide a limitation of the base current. In addition, a bipolar control transistor leads to higher waste voltages than a MOS transistor with a smaller linearity range. This is particularly disadvantageous in the case of portable type devices for which it is desirable to minimize the waste voltage, i.e. to make it, preferably, less than 200 mV.

The present invention aims to provide a linear regulator that overcomes the disadvantages of known circuits.

The present invention aims in particular to provide a linear regulator which has a reduced waste voltage.

The present invention aims to provide such a regulator that can be manufactured using a standard MOS die.

To achieve these and other objects, the present invention provides a linear regulator having an output stage comprising first and second P-channel MOS transistors connected in series between a first DC power terminal and an output terminal providing an output terminal. regulated output voltage, and a control circuit of the first and second transistors capable of providing first and second control signals as a function of the output voltage and the voltage at the midpoint of the series connection.

According to an embodiment of the present invention, the control circuit comprises an input / output circuit and a reference circuit, the input / output circuit having a first input, receiving a first voltage setpoint provided by said reference circuit; a second input, connected to said output terminal; a third input receiving a second voltage setpoint supplied by said reference circuit; a fourth input connected to said midpoint; a first output connected to the gate of the first transistor; and a second output connected to the gate of the second transistor.

According to an embodiment of the present invention, the input / output circuit is a dual differential comparator with four inputs and two outputs.

According to an embodiment of the present invention, the input / output circuit comprises first and second differential comparators with two inputs and two outputs, the input terminals of the first differential comparator being the first and second input terminals of the input comparator. an input / output circuit and its output being the second output of said input / output circuit; and the input terminals of the second differential comparator being the third and fourth input terminals of said input / output circuit and its output being the first output.

According to one embodiment of the present invention, the first differential comparator comprises an input / output stage and an output stage, said input / output stage comprising two differential branches, each of which comprises a P-channel MOS transistor connected in parallel. series with a first N-channel MOS transistor, the sources of the P-channel transistors being interconnected to an output terminal of a current source whose input terminal is connected to said DC power terminal, the sources of the first N-channel transistors being interconnected to a ground terminal, the gates of said first N-channel MOS transistors being interconnected, the gates of the P-channel transistors constituting the first and second input terminals of the input / output circuit, the gate of the first N-channel MOS transistor of the branch having the first input being connected to its drain, the intermediate connection point of the drains of the complementary transistors of the other branch being connected to the gate of a second N-channel MOS transistor connected in said output stage, in series between the power supply terminals, with a first impedance, the midpoint of the series connection of said first impedance and the second transistor constituting the output terminal of said first differential comparator.

According to one embodiment of the present invention, the second differential comparator comprises two symmetrical differential branches each consisting of the series connection of a second impedance, and a third N-channel MOS transistor, respectively, the sources of the third transistors. N-channel transistor being interconnected to the drain of a fourth N-channel MOS transistor having its source connected to ground, the gate of the fourth N-channel transistor being connected to the gate of the second N-channel MOS transistor of the N-channel stage; output of the first differential comparator.

• la figure 1, qui a été décrite précédemment, représente de façon partielle et schématique la structure d'un régulateur linéaire connu associé à une charge ;
• les figures 2A à 2C, qui ont été décrites précédemment, sont des chronogrammes illustrant le fonctionnement du régulateur de la figure 1 ;
• la figure 3 représente, sous forme d'un schéma-blocs partiel et schématique, un régulateur linéaire selon un mode de réalisation de la présente invention associé à une charge ;
• la figure 4A est un chronogramme illustrant une première consigne de tension du régulateur de la figure 3 ;
• la figure 4B est un chronogramme illustrant la tension de sortie du régulateur de la figure 3 ;
• la figure 4C est un chronogramme illustrant une deuxième consigne de tension du régulateur de la figure 3 ;
• la figure 4D est un chronogramme illustrant une tension aux bornes d'un composant d'un étage de sortie du régulateur de la figure 3 ;
• la figure 5 représente, partiellement et schématiquement, un mode de réalisation d'un étage d'entrée/sortie du régulateur de la figure 3 ; et
• la figure 6 représente un mode de réalisation d'un générateur de première et deuxième consignes de tension utilisable dans le régulateur de la figure 3.

These and other objects, features, and advantages of the present invention will be set forth in detail in the following description of particular embodiments given as a non-limiting example in connection with the accompanying drawings in which:

• the figure 1 , which has been previously described, partially and schematically represents the structure of a known linear regulator associated with a load;
• the FIGS. 2A to 2C , which have been described previously, are timing diagrams illustrating the operation of the regulator of the figure 1 ;
• the figure 3 represents, in the form of a partial and schematic block diagram, a linear regulator according to an embodiment of the present invention associated with a load;
• the Figure 4A is a timing diagram illustrating a first voltage setpoint of the regulator of the figure 3 ;
• the Figure 4B is a timing diagram illustrating the output voltage of the regulator of the figure 3 ;
• the figure 4C is a timing diagram illustrating a second voltage setpoint of the regulator of the figure 3 ;
• the figure 4D is a timing diagram illustrating a voltage across a component of an output stage of the regulator of the figure 3 ;
• the figure 5 represents, partially and schematically, an embodiment of an input / output stage of the regulator of the figure 3 ; and
• the figure 6 represents an embodiment of a generator of first and second voltage setpoints usable in the regulator of the figure 3 .

For the sake of clarity, the same elements have been designated in the various figures by the same references. In addition, only the elements that are necessary for the understanding of the present invention have been shown. Thus, any validation circuits of the reference voltage generators are neither represented nor described.

The figure 3 represents, in the form of a block diagram, a linear regulator 30 according to an embodiment of the present invention. The regulator 30 comprises an output stage 31 consisting of the series connection, between a high power supply rail Vdd and an output terminal OUT, of two P-channel MOS transistors 32 and 33. The output terminal OUT is intended for to be connected to a first power supply terminal of a load (LD) 1, a second power supply terminal of which is connected to a low supply rail or ground GND. To quickly stabilize the regulated output voltage, the linear regulator 30 also preferably includes a stabilization impedance 11, for example a capacitor C.

The regulation of the voltage Vout across the terminals of the load 1, that is to say on the output terminal OUT, is effected by modulating control signals of the gates G1 and G2 of the transistors 32 and 33, respectively, so as to modify their transconductance.

The control signals of the output stage 31 are produced by a control circuit 35. The circuit 35 modulates the control signal of the gate G1 of the transistor 32 so as to regulate the voltage at the midpoint MID of the series connection. transistors 32 and 33 of the output stage 31. It also modulates the control signal of the gate G2 of the transistor 32 so as to regulate the output voltage Vout. The circuit 35 includes an input / output stage (IN / OUT) 36 for generating the control signals and a reference stage (REF) 37. The input / output stage 36 comprises four input terminals I1 , I2, I3 and I4 and two output terminals O1 and O2. The terminal I1 receives a regulation voltage setpoint V1 of the output voltage Vout. The terminal I2 receives the output voltage Vout. The terminal I3 receives a regulation voltage setpoint V2 of the voltage at the MID midpoint. The terminal I4 receives the voltage Vmid of the midpoint MID by a direct connection at this point. The output terminals O1 and O2 are respectively connected to the gates G1, G2.

The regulation setpoints V1 and V2 received on the terminals I1 and I3 of the stage 36, respectively, are provided by the reference circuit (REF) 37 from a variable voltage source 38 (Vreg). More particularly, in order to regulate the MID midpoint so as to guarantee an equipartition of the voltages across each of the two series transistors 32 and 33, the regulation setpoint V2 of the MID midpoint is equal to half the sum of the voltage. high power supply Vdd and the first regulation setpoint V1 (V2 = (Vdd + V1) / 2). The source 38 therefore preferably provides directly the first setpoint V1 (Vreg = V1) from which the circuit 37 supplies the second setpoint V2 according to the preceding relation.

The FIGS. 4A, 4B, 4C and 4D respectively illustrate, by timing diagrams, the variation as a function of time t of the regulation setpoint V1 of the output voltage Vout of regulator 30 of the figure 3 , the output voltage Vout, the regulation setpoint V2 of the mid-point voltage MID and the current voltage Vmid at the midpoint MID, that is to say the drain voltage of the transistor 32.

When starting the regulator 30, at a time t10, the reference circuit 37 is enabled by a start of the source 38 and produces the regulation setpoints V1 and V2. As illustrated by Figures 4A and 4C , the regulation setpoints V1 and V2 are, during a priming phase (times t10 to t11), parallel ramps. Indeed, as previously indicated, to ensure a balance of the distribution of the voltages across the transistors 32 and 33, it must be ensured that at all times the potential at the MID midpoint is equal to half the difference between the high supply voltage Vdd and the voltage Vout across the load 1 (Vmid = (Vdd-Vout) / 2). To do this, it is necessary to apply a setpoint equal to the half-sum of the high supply voltage Vdd and the first setpoint V1. When the setpoint V1 is changed from a zero value to a nominal setpoint Vref, the control circuit 35 must be able to provide such a condition. To allow a linear tracking, it is then preferable that the setpoint V1 varies slowly rather than abruptly as in the case of a standard setpoint ( Figure 2A ).

As illustrated by Figure 4B during the priming phase, the output voltage Vout follows, from time t10, the first setpoint V1 until it stabilizes at time t11 at the nominal value Vref. The voltage Vmid at the midpoint MID, illustrated in figure 4D on the other hand, decreases in a controlled way from half of the high power supply (Vdd / 2) to the stable value (Vdd-Vref) / 2. In nominal operation, between instants t11 and t12, the output voltages Vout and the midpoint Vmid are kept stable by stable setpoints V1 and V2. During an extinguishing command of the load 1 at a time t12, to allow a linear follow-up of the second setpoint V2, the first setpoint V1 is progressively reduced to zero along a ramp until a time t13. The supply Vdd is then distributed symmetrically on the transistors 32 and 33.

At nominal speed (from t11 to t12), the control circuit 35 ensures that any fluctuation of the power at the level of the load 1 results in a variation of the setpoints V1 and V2 so as to restore the rated speed and to distribute the power variation symmetrically on the two power transistors 32 and 33. Thus, neither of the two transistors 32 and / or 33 is confronted with an excessive drain / source voltage.

We have shown in figure 4 ramps of initiation and extinction of respective slope different. More particularly, there is shown a faster extinction (t12-t13) than the boot (t10-t11). In practice, the slope of the ramps depends on the technical performance of the circuits and in particular the capacity of the control circuit 35 to follow, transform and transmit, the variation of the first setpoint V1. Slopes may be faster or slower than represented. In addition, they may be symmetrical or have an asymmetry inverse to that shown, that is to say that the boot can be faster than extinction.

The figure 5 illustrates, schematically and partially, the structure of an embodiment of the input / output stage 36 of a control circuit 35 of an output stage 31 of a regulator 30 according to the present invention.

The input / output circuit 36 with four inputs and two outputs is a differential comparator. More particularly, the circuit 36 consists of the combination of a first differential comparator 50 and a second differential comparator 51 interlaced in the following manner.

The first comparator 50, delimited by a dotted frame in figure 5 , is intended to regulate the output voltage Vout from the first setpoint V1. The comparator 50 therefore has a structure similar to that of a comparator known differential such as comparator 3 described in connection with the figure 1 . For the sake of clarity, the structure of the comparator 50 is described below using the same references as in figure 1 .

The comparator 50 comprises an input / output stage 4 and an output stage 5. The stage 4 comprises two differential branches each comprising a P-channel MOS transistor 61, 62 connected in series with an N-channel MOS transistor 63, The sources of transistors 61 and 62 are connected to an output terminal of a current source 60 having an input terminal connected to the high power supply Vdd. The sources of transistors 63 and 64 are connected to the low GND supply. The gates of transistors 63 and 64 are interconnected. The gate of transistor 61 constitutes terminal I1 and receives setpoint V1. The gate of the transistor 63 is connected to its drain, that is to say also to the drain of the transistor 61. The gate of the transistor 62 constitutes the terminal I2 and receives the current voltage Vout across the load 1 by a connection to the output terminal OUT of the controller. The connection point 65 of the drains of the transistors 62 and 64 constitutes the output of the input / output stage 4 of the comparator 50.

The output stage 5 consists of the series connection, between the high power supply Vdd and the ground GND, of an impedance 9, preferably resistive (R), and an N-channel MOS transistor 10. The point of connection of the impedance 9 and the transistor 10 constitutes the output terminal 02 providing the control signal of the gate G2 of the transistor 33. The gate of the transistor 10 is connected to the midpoint 65 of the differential branch 62-64 of the entrance floor 4.

The second differential comparator 51 is intended to control the regulation of the voltage at the MID point. It supplies on the output terminal 01 the control signal of the gate G1. The second comparator 51 comprises two symmetrical differential branches each consisting of the series connection of an impedance 52, 53, preferably resistive, and a N-channel MOS transistor 54, 55, respectively. The sources of transistors 54 and 55 are connected to the drain of an N-channel MOS transistor 56 whose source is connected to ground GND. The gate of the transistor 56 is connected to the output 65 of the input / output stage 4 and to the gate of the transistor 10 of the output stage 5 of the first differential comparator 50. Therefore, the operating point of the second The differential comparator 51 depends on that of the output stage 5 of the first differential comparator 50. This makes it possible to stabilize the control signal of the gate G1 of the transistor 32 by at most a required level, which depends on the level of the control signal. the gate G2 of the transistor 33 supplied by the first comparator 50. In particular, when the load 1 is disabled and the transistor 33 is open, the transistor 56 will be completely on and allow a control of the gate G1 own to limit the voltage Vmid at half (Vdd / 2) of the high feed, as has been described previously in relation to the figure 4 . The gates of the transistors 54 and 55 constitute, respectively, the terminals I3 and I4 for applying the voltages V2 and Vmid.

The figure 6 represents, schematically and partially, an embodiment of a generator 37 of the instructions V1 and V2. The reference circuit 37 is, according to an embodiment of the present invention, a resistive voltage divider. The resistive divider comprises the series connection between the high supply rails Vdd and low GND of three successive resistors 71, 72 and 73. The connection point 74 of the resistors 72 and 73 is the output terminal of a differential comparator 75 two inputs and one output, for example similar to the comparator 3 of the figure 1 . The non-inverting input terminal of the comparator 75 receives the regulation setpoint Vreg of the output voltage Vout of the regulator 30, for example, by a connection to the source 38. The inverting input terminal of the comparator 75 is connected to the output terminal 74. Thus, it copies to the terminals of the resistor 73 the first set point V1. By choosing resistors 71 and 72 of the same values, the midpoint of these two resistors is controlled linearly by the comparator 75 to the desired value V2 of the half-sum of the supply voltage and the first setpoint V1.

The present invention advantageously provides a linear power regulator fully achievable by a low voltage standard MOS die and small dimensions. Indeed, the replacement of the high voltage MOS transistor known regulators by two low voltage transistors reduces the integration surface. In addition, the surface increase of the control portion relative to the control circuit of a known regulator is negligible compared to the surface gain associated with the change of power switch.

In addition, the linear regulator according to the present invention has a lower voltage drop than known regulators. By way of nonlimiting example, if the high supply voltage Vdd is from 3.3 to 5.5 volts, each transistor 32 and 33 of the output stage 31 of the linear regulator 30 of the present invention is a transistor Standard MOS clean to hold a drain / source voltage of about 2.5 volts. The regulator's waste voltage is then reduced to values of the order of 200 mV.

Of course, the present invention is susceptible of various variations and modifications which will be apparent to those skilled in the art. In particular, it will be noted that the capacitor C (impedance 11) for stabilizing the output voltage Vout has been described as being functionally part of the linear regulator 30. In practice, the capacitance value of the capacitor C is relatively high and varies in depending on the application, that is to say the load 1. The capacitor C is therefore preferably made outside an integrated circuit chip comprising the entire regulator 30, and is mounted directly in parallel on the load 1. Moreover, the skilled person will modify the characteristics of the various components to the die used.

Claims (6)

1. A linear regulator having an output stage (31) comprising first and second P-channel MOS transistors (32, 33) serially connected between a first D.C. supply terminal (Vdd) and an output terminal (OUT) providing a regulated output voltage (Vout), and a control circuit (35) for controlling the first and second transistors, characterized in that the control circuit is capable of providing them with first and second control signals as a function of the output voltage and the voltage at the midpoint (MID) of the series connection, so that the voltage at the midpoint is maintained at half the difference between the D.C. supply and the regulated output voltage.
2. The regulator according to claim 1, characterized in that the control circuit (35) comprises an input/output circuit (36) and a reference circuit (37), the input/output circuit comprising:

   a first input (I1), receiving a first voltage reference (V1) provided by said reference circuit;

   a second input (I2), connected to said output terminal (OUT);

   a third input (I3) receiving a second voltage reference (V2) provided by said reference circuit;

   a fourth input (14) connected to said midpoint (MID);

   a first output (O1) connected to the gate (G1) of the first transistor (32); and

   a second output (02) connected to the gate (G2) of the second transistor (33).
3. The regulator according to claim 2, characterized in that the input/output circuit (36) is a double differential comparator with four inputs and two outputs.
4. The regulator according to claim 2, characterized in that the input/output circuit (36) comprises first (50) and second (51) differential comparators with two inputs and two outputs, the input terminals of the first differential comparator being the first (I1) and second (I2) input terminals of the input/output circuit and its output being the second output (O2) of said input/output circuit; and the input terminals of the second differential comparator being the third (I3) and fourth (I4) input terminals of said input/output circuit and its output being the first output (O1) thereof.
5. The regulator according to claim 4, characterized in that the first differential comparator (50) comprises an input/output stage (4) and an output stage (5), said input/output stage comprising two differential branches, each of which comprises a P-channel MOS transistor (61, 62) connected in series with a first N-channel MOS transistor (63, 64), the sources of the P-channel transistors being interconnected with an output terminal of a current source (60) having an input terminal connected to said D.C. supply terminal (Vdd), the sources of the first N-channel transistors being interconnected with a ground terminal (GND), the gates of the first N-channel MOS transistors being interconnected, the gates of the P-channel transistors forming the first (I1) and second (I2) input terminals of the input/output circuit (36), the gate of said first N-channel MOS transistor of the branch (61-63) comprising the first input being connected to its drain, the midpoint (65) of connection of the drains of the complementary transistors of the other branch (62-64) being connected to the gate of a second N-channel MOS transistor (10) connected, in said output stage (5), in series between the supply terminals, with a first impedance (9), the midpoint of the series connection of said first impedance and of the second transistor forming the output terminal (O2) of said first differential comparator.
6. The regulator according to claim 5, characterized in that the second differential comparator (51) comprises two symmetrical differential branches, each formed of the series connection of a second impedance (52, 53) and of a third N-channel MOS transistor (54, 55), respectively, the sources of the third N-channel transistors being interconnected with the drain of a fourth N-channel MOS transistor (56) having its source connected to ground (GND), the gate of the fourth N-channel transistor being connected to the gate of the second N-channel MOS transistor (10) of the output stage (5) of the first differential comparator (50).

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