DE3853963D1 - Basiszelle für eine Gatematrixvorrichtung. - Google Patents
Basiszelle für eine Gatematrixvorrichtung.Info
- Publication number
- DE3853963D1 DE3853963D1 DE3853963T DE3853963T DE3853963D1 DE 3853963 D1 DE3853963 D1 DE 3853963D1 DE 3853963 T DE3853963 T DE 3853963T DE 3853963 T DE3853963 T DE 3853963T DE 3853963 D1 DE3853963 D1 DE 3853963D1
- Authority
- DE
- Germany
- Prior art keywords
- matrix device
- base cell
- gate matrix
- gate
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000011159 matrix material Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/903—Masterslice integrated circuits comprising field effect technology
- H10D84/907—CMOS gate arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62059476A JPS63278248A (ja) | 1987-03-13 | 1987-03-13 | ゲ−トアレイの基本セル |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3853963D1 true DE3853963D1 (de) | 1995-07-20 |
DE3853963T2 DE3853963T2 (de) | 1996-03-14 |
Family
ID=13114394
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3853963T Expired - Fee Related DE3853963T2 (de) | 1987-03-13 | 1988-03-11 | Basiszelle für eine Gatematrixvorrichtung. |
Country Status (5)
Country | Link |
---|---|
US (1) | US5031018A (de) |
EP (1) | EP0282082B1 (de) |
JP (1) | JPS63278248A (de) |
KR (1) | KR910001424B1 (de) |
DE (1) | DE3853963T2 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5670816A (en) * | 1989-04-07 | 1997-09-23 | Kabushiki Kaisha Toshiba | Semiconductor device |
JP2714723B2 (ja) * | 1991-03-15 | 1998-02-16 | シャープ株式会社 | 半導体集積回路装置の製造方法 |
JP3186084B2 (ja) * | 1991-05-24 | 2001-07-11 | 日本電気株式会社 | 半導体メモリー装置 |
EP0690509A1 (de) * | 1994-06-30 | 1996-01-03 | Texas Instruments Incorporated | Substratanschluss für eine Gate-Array-Basiszelle und Verfahren zu ihrer Herstellung |
EP1045446A3 (de) * | 1994-09-30 | 2000-11-15 | Yozan Inc. | MOS-Inverter mit einer verengten Kanalbreite |
IT1289933B1 (it) * | 1997-02-20 | 1998-10-19 | Sgs Thomson Microelectronics | Dispositivo di memoria con matrice di celle di memoria in triplo well e relativo procedimento di fabbricazione |
JP3061004B2 (ja) * | 1997-06-18 | 2000-07-10 | 日本電気株式会社 | 半導体装置 |
JP3006548B2 (ja) * | 1997-06-23 | 2000-02-07 | 日本電気株式会社 | Mos型半導体読み出し専用メモリ装置 |
US6071778A (en) * | 1998-02-20 | 2000-06-06 | Stmicroelectronics S.R.L. | Memory device with a memory cell array in triple well, and related manufacturing process |
JP4794030B2 (ja) * | 2000-07-10 | 2011-10-12 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US7402846B2 (en) * | 2005-10-20 | 2008-07-22 | Atmel Corporation | Electrostatic discharge (ESD) protection structure and a circuit using the same |
US9837353B2 (en) | 2016-03-01 | 2017-12-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Middle end-of-line strap for standard cell |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5851539A (ja) * | 1981-09-22 | 1983-03-26 | Nec Corp | 集積回路装置 |
JPS5851939A (ja) * | 1981-09-24 | 1983-03-26 | Chiyoda Chem Eng & Constr Co Ltd | 重質炭化水素油水素化処理用多孔質担体の製造方法 |
US4430583A (en) * | 1981-10-30 | 1984-02-07 | Bell Telephone Laboratories, Incorporated | Apparatus for increasing the speed of a circuit having a string of IGFETs |
NL8301629A (nl) * | 1983-05-09 | 1984-12-03 | Philips Nv | Halfgeleiderinrichting. |
JPH0828480B2 (ja) * | 1983-09-30 | 1996-03-21 | 富士通株式会社 | 半導体集積回路装置 |
JPS60152055A (ja) * | 1984-01-20 | 1985-08-10 | Matsushita Electric Ind Co Ltd | 相補型mos半導体装置 |
EP0166386A3 (de) * | 1984-06-29 | 1987-08-05 | Siemens Aktiengesellschaft | Integrierte Schaltung in komplementärer Schaltungstechnik |
-
1987
- 1987-03-13 JP JP62059476A patent/JPS63278248A/ja active Pending
-
1988
- 1988-03-10 US US07/166,488 patent/US5031018A/en not_active Expired - Fee Related
- 1988-03-11 DE DE3853963T patent/DE3853963T2/de not_active Expired - Fee Related
- 1988-03-11 EP EP88103900A patent/EP0282082B1/de not_active Expired - Lifetime
- 1988-03-12 KR KR1019880002582A patent/KR910001424B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US5031018A (en) | 1991-07-09 |
KR880011923A (ko) | 1988-10-31 |
KR910001424B1 (ko) | 1991-03-05 |
JPS63278248A (ja) | 1988-11-15 |
DE3853963T2 (de) | 1996-03-14 |
EP0282082B1 (de) | 1995-06-14 |
EP0282082A2 (de) | 1988-09-14 |
EP0282082A3 (en) | 1990-07-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |