DE2415736A1 - METAL-SILICON FIELD EFFECT TRANSISTOR - Google Patents

Description

DIFLOM-INtJENIEUH / «« 1

KARL-HEINZSCHAUMBURG ZH I

PATKNTANWAIiT

fSSr ^ i , Λ 8 MUNICH «,

10900 North Tantau Avenue mauehkihchühbth. egg

Cupertino, California 95014 amawm «a mim · USA _m IJ? 1274

Metal-silicon pelde effect transistor

The most varied types of field effect transistors or arrangements have been developed in transistor technology. Very spacious becomes the metal-on-silicon field effect transistor used, which is commonly referred to as MOSFET. There is also the complementary combination of N-channel and P-channel MOSFETs on a single circuit carrier, also commonly referred to as CMOS. These areas of application such arrangements and their various advantages are known to those skilled in the art. A typical N-channel MOSFET can be a (P -) - Zone, which is introduced into the upper surface of an (N -) - substrate and two (N +) - channels with mutual Distance Contains · A gate electrode is on top of an insulating layer on the top surface of the substrate applied between the two (N +) - channels, and generally these two channels are surrounded by an insulation P +. the Such a MOSFET can function by applying a signal voltage to one of the (N +) channels and by connecting of the other channel can be caused by a load resistor with earth potential. The first channel is then called Source, the second called drain. The (P-) zone is normally with the negative operating voltage (-V_ "),

Cw

the substrate with the positive operating voltage (+ V._)

· ■■ * · "cc

bund en · 'This arrangement is controlled by applying a control voltage to the gate electrode.

409843/0776

The previously common MOSFET and CMOS arrangements cause various difficulties and are subject to limitations. For example, a forward polarity between source and body or between drain and body must be avoided in its operation. This forward polarity could arise from an overvoltage as a result of a compensation process at the source or drain and could also be formed by applying a signal voltage before the negative operating voltage -V _{cc is connected} to the (P -) zone. Such a condition creates a transistor effect by which a base current is created through the grounded (P-) region and the (N-) substrate acts as a collector so that the collector current is limited only by the resistance of the substrate. This is very likely to damage the transistor.

It should also be noted that under many normal operating conditions of MOSFET arrangements, the gate-source threshold voltage required to generate the conductive state according to the enhancement principle is so high that a further power supply device in addition to the normally provided power supply for the MOSFET arrangement is required·

The object of the invention is now the MOSFET arrangements to improve so that a protection against overvoltages and against switch-on processes, a lower switching threshold voltage and a lower drain-source resistance are guaranteed with less space required for the circuit carrier.

The solution to this problem provided according to claim 1 can be used in the same way for N-channel and P-channel MOSFET arrangements , and the following description relates to N-channel arrangements, their conductivity types and polar

409843/0776

would only have to be reversed to get the appropriate To enable application for P-channel arrangements. The invention works on the principle that the (P -) zone of an N-channel MOSFET is held electrically floating. There is therefore no electrical connection to the (P -) zone. The (N -) - Subetrat is connected to the operating voltage + V, while the Source, drain and gate electrodes are wired as in a MOSFET of the usual type, so that an inner Diode path is present in the reverse direction within the body of the overall arrangement. This then creates the possibility a transistor effect between a channel, the (P-) - zone and the substrate prevents, since no possible source for Base current of such a transistor arrangement is available. Therefore it is not necessary when using a single MOSFET according to the invention in other circuits protection against forward polarity, for example to be provided between source and body. Furthermore, a much lower voltage function is required according to the enhancement principle, so that internal measures to compensate for the body effect of the MOSFET are not required. Integrated Circuits with MOSFETS of the usual type normally contain a multiplicity of such devices, a single one Fulfill function, since the compensation of body effects is required. The invention only requires one single MOSFET per function, which then has the advantage of a much greater storage density in integrated circuits realized.

The invention also avoids concatenated blocking phenomena in CMOS technology, in the case of N-channel and P-channel arrangements are provided on a single circuit carrier. Even though an arrangement according to the invention with the principle of electrically floating circuit described, the number of possible Ways for such locking phenomena are essential

409843/0776

is reduced by keeping the base current to a minimum it is possible that combined N- and P-channel arrangements on a CMQS substrate create an NPNP or PNPN situation, which has as an equivalent a controlled silicon rectifier «This undesirable effect can be switching errors and possible Cause destruction of the entire arrangement. The invention makes it possible with a combination of N-channel and P-channel arrangements on a CMOS substrate in addition to the electrically floating function of the (P -) - zone initially one Provide N-epitaxial layer on the substrate and in Contact with and under the (P-) zone a so-called buried layer P + is to be provided, which is in a trough-shaped manner in both Layers reach in. This buried layer P +, which is also referred to as the tub layer in the following, maintains the service life of minority charge carriers that are available from the (P -) zone, and thus a possible undesirable transistor effect or SCR effect minimal.

Embodiments of the invention are set out below Hand of the figures described. Show it:

Fig. 1 shows the electrical circuit principle of a MOSFET of known type,

2 shows a schematic sectional illustration of a MOSFET according to the invention,

FIG. 2 shows the electrical circuit of a MOSFET according to FIG. 2 and

Fig · 4 is a schematic sectional view of an N-channel and a P-channel MOSFET in CMOS technology according to the invention.

In Fig. 1 is the electrical circuit of an N-channel MOSFET of known type, the body B, which represents the (P -) zone, connected to the operating voltage -V

409843/0776

is. The source, drain and gate electrodes are labeled S, D, G, and the drain electrode is connected to ground potential _{via a load resistor R T.} Furthermore,

Ii

dead voltages specified, the signal voltage has a value of +10 volts, the voltage -V has a value of -15 volts and the gate voltage has a value of +15 volts · Under these conditions is applicable

^V GS " ^15V " ^10V " ^{+ 5V} and

V _BS - -15V - 10V - -25V

If you now consider the gate-source threshold voltage and define for it the value X with a base-source voltage of -25 volts and a value of Y with a base-source voltage of 0 volts, then approximately X » Y + 2.5 \ / V _BS apply. If you insert the corresponding value for V ₅₃ , the result is X ■ »Y + 12.5 * It can therefore be seen that even with a gate-source threshold voltage Y of 1 volt to 3 volts, for example with a Basls source -Voltage of 0 volts the quantity X, which is the gate-source threshold voltage with a base-source voltage of 25 volts, is in the range of 13.5 volts to 15.5 volts. Under these circumstances, a gate voltage of at least 23.5 volts to 25.5 volts is required in order to switch on the arrangement in the event of a puncture according to the enhancement principle. Such a high gate voltage requires an additional power supply in normal circuits, since usually at most about 15 volts are available in integrated circuits. The invention avoids these difficulties, among others to be described.

In Pig. 2 the physical structure of an arrangement according to the invention is now shown. This has an (N-) substrate 21, which in practice is part of a silicon circuit carrier is the one with a light doping of donor impurities is provided. A (P-) zone 13 is provided in the upper surface of the substrate, which is thereby formed can that an acceptor contamination in the circuit board is diffused. This zone has such a lateral extent that several additional areas are provided in it can be. In the (P-) zone on the upper surface of the circuit board there are two (N +) channels at a distance from one another 23 and 24 provided. These form areas with relative heavily doped with donor impurities. The channels

23 and 24 are surrounded by a (P +) insulating area 26.

There is an insulating layer on the upper surface of the circuit board 31 formed, which consists for example of silicon oxide on a silicon carrier. With this insulating layer a first opening is provided above the (N +) channel 23, which is filled with metal such as * aluminum. This forms a souroe electrode 32, which is in ohmic connection with the channel. A second opening is above the (N +) channel 24 and forms a drain electrode 33 · Above the insulating layer 31 is between the two channels 23 and

24 a metal electrode J> k is arranged, which forms the gate electrode. Electrical conductors are connected to electrodes 32, 33 and 34 and are used for wiring. According to the invention, the substrate 21 is connected to the positive operating voltage + V, which normally has a value of +15 volts. A metal contact surface 36 is used for this purpose. The (P -) zone is not connected because it is kept floating electrically.

The electrical configuration of the arrangement shown in FIG. 2 is shown in FIG. 3, with the source, drain and gate electrodes corresponding to those shown in FIG. 2. The contacts are labeled in the same way as in FIG Fig. 3 is the positive operating voltage + V _n . with the (N -) -

GC

Substrate connected, and within the array is one Diode 41 is provided, which conducts towards the (N-) substrate. This diode 41 is made by the PN junction between the (P-) zone and the (N-) substrate. The consequence of this difference between the invention and known arrangements is very far-reaching. In this context, reference is made to the above description of the arrangement according to FIG. 1 referenced. If you take into account for Fig. 3 * that the same potential values are used, i.e. an input signal voltage of +10 volts at the source electrode, a gate voltage of + 15 volts and an operating voltage V__ of +15 volts, it can be seen that a gate

CC

Source threshold voltage from 1 volt to 3 volts with a base-source voltage from 0 volts produces a strong line>, since the applied gate-source voltage is +5 volts. Under these circumstances the gate voltage only needs to be 11 volts to 13 volts with a base-source voltage of 10 volts, to turn on the arrangement. Using the example described above, it can be seen that this voltage is approximately 12.5 Volts is lower than that required by the normal and customary arrangements under the same circumstances. By the invention makes it possible to use conventional +15 volt power supplies, as they are generally intended for operational amplifiers, also to be used here, so that in contrast to the previously known principles no additional power supply is required.

It should be noted in particular that the internal diode 41 in a MOSFET arrangement according to the invention and the electrical floating state of the (P -) - zone in the

409843/0776

N-channel MOSFET described as an example the possibility of Transistor action from an N-channel through the (P-) zone to the (N -) - substrate is excluded. With this configuration it is not possible to get the equivalent of a base current for a to produce such a transistor effect, so that accordingly no conductivity occurs which can destroy the arrangement. In addition, unlike the prior art arrangements, high voltage power supplies are not required. Since its own Protection of the arrangement against errors caused by signal equalization processes or unsuitable operating switch-on is provided, no additional switching elements are required for such protection. A typical output circuit in CMOS technology can include four MOSFET arrays for processing a logic signal, while the invention only uses a single one MOSFET enables a corresponding circuit. Therefore, a saving in circuit board area is increased by the factor 4: 1 is achieved, and there are also significant advantages due to the simpler manufacture of integrated circuits. Besides, be notes that the drain-source resistance in the conductive or switched-on state of the device in many cases through the invention is significantly reduced, it is usually 1/10 of the resistance of conventional MOSFET arrangements.

As stated above, in the invention, an undesirable effect corresponding to a controlled silicon leveler can additionally be avoided. In this regard, reference is made to Fig. 4, which shows an N-channel MOSFET and a P-channel MOSFET on a single substrate 51 which is an (N-) substrate. An N-epitaxial layer 52 is formed on this substrate in a known manner, as a result of which a buried layer 53 of heavily doped acceptor material is formed in the epitaxial layer 52 by means of masks and diffusion, specifically within the volume provided as N-channel MOSFET 54 » The (P -) - zone 56 is above and in con-

409843/0776

clock with the (P +) - buried layer 53 and contains several (N +) - areas 57 to 60, the source and drain areas of the MOSPET 54 are. The two (N +) areas 57 and 59 can electrically outside of the circuit substrate connected to one another to a source electrode 6l, while the two other (N +) regions 58 and 60 are connected together to a drain electrode 62. In connection with FIG. 4 a gate electrode 63 is also shown schematically, which is connected to the two gate regions between adjacent (N +) channels 57 to 60 is connected. Only the areas within the switching element shown are described.

The P-channel MOSPET 64 contains several (P +) channels 66 to 69, extending from the top surface of the element into epitaxial layer 52 and with connections to source and drain electrodes 71 and 72 are provided. A gate electrode 73 leads to metal gate areas above and between adjacent (P +) channels 66 to 69.

The undesirable effect of the silicon controlled rectifier, which is minimized by the invention, could occur between the N-channel arrangement and the P-channel arrangement and is a result of the gain product of a vertical NPN situation in the N-channel arrangement and a horizontal PNP situation in the P-channel arrangement if this is greater than 1. A vertical NPN transistor is formed with the (N +) channel 60 as the emitter, the (P-) zone 56 and the (P +) buried layer 53 as the base and the N-epitaxial layer 52 as the collector. The PNP transistor effective in the lateral direction has the (P +) channel 66 as the emitter, the N-epitaxial layer 52 as the base and the (P-) zone 56 and the (P +) -buried layer 53 as the collector. It can thus be seen that it is a four-layer arrangement with a structure corresponding to a controlled silicon

409843/0776

rectifier acts. A circuit analysis shows that the corresponding switching effect can only occur if the product of the gains (β) of the two transistor paths is greater than or equal to 1. However, the invention avoids this effect or at least limits it to such a low level that it does not have any harmful effects. The gain of the NPN transistor is reduced so that the total gain is less than one. This is achieved by the (P +) buried layer 55 made of heavily doped acceptor material, which drastically reduces the service life of excess minority charge carriers in the base of the NPN transistor. This in turn reduces the gain of the NPN transistor, which is directly proportional to the life of the minority charge carriers. An undesirable switching effect corresponding to a controlled silicon rectifier from the simulation of a four-layer arrangement in CMOS technology is thus practically avoided, since the (P +) buried layer is present in the switching element, the N-epitaxial layer making it easier to arrange such a region during manufacture.

All of the above explanations also relate in the same way to P-channel MOSFETS, as explained at the beginning became. The same applies to the various possible developments of the invention.

409843/0776

Claims (5)

- li - lj metal-silicon field effect transistor arrangement with a Substrate of a first conductivity type, a zone of a second conductivity type provided on the surface of the substrate « in which source and drain regions of the first conductivity type are arranged at a mutual distance « an insulating layer covering all surfaces of the transistor arrangement and one on top of this between the source -. ' Gate electrode arranged in drain regions, characterized in that the source region (23), the drain region (24), the gate electrode (34) and the substrate (21) with contact electrodes are connected. 2. Transistor arrangement according to claim 1, characterized in that the substrate (21) is lightly doped that the zone (22) of the second conductivity type is lightly doped that the source and drain regions (23, 24) are heavily doped and that the insulating layer (31) consists of silicon oxide and covers all surfaces of the substrate (21). 3. Transistor arrangement according to claim 2, characterized in that the substrate (21) with its contact electrode on the the surface facing away from the zone (22) of the second conductivity type is provided. 4. In CMOS technology constructed transistor arrangement according to one of the preceding claims, characterized by an (N -) - substrate (51)> an N-epitaxial layer arranged on the substrate (51) (52), which has a (P +) - buried layer (53), one between, the (P +) - buried layer (53) and an upper one Area of the N-Epltaxialsoicht (52) arranged (P -) - zone, 409843/0776 at least two (N +) channels (58, 59) in the upper surface of the (P-) region (56), which form source and drain regions, a metal-on-silicon gate electrode (63) between the Source and drain regions (58, 59) have at least two (P +) channels (67, 68) which are laterally offset to the (N +) channels (58, 59) are embedded in the N-epitaxial layer (52) and form P-channel source and drain regions between .den at least one metal-on-silicon gate electrode (73) is arranged, and one connected to the substrate (5I) Body contact as connection electrode (B). 5. Operating method for a transistor arrangement according to One of the preceding claims, characterized in that a positive signal is sent to the source electrode (32) and a positive operating voltage (-V "_) to the N-substrate (21) and a positive control voltage to the gate electrode (34) voltage is turned on, whereby a drain current flows through a load resistor (R _L ) connected to the drain electrode (33). 409043/077 Blank page