CN1917173A - Fabrication method of gate dielectric layer - Google Patents

Abstract

A method for manufacturing a gate dielectric layer includes providing a substrate, which is divided into at least a high voltage circuit region and a low voltage circuit region. Then, a first dielectric layer is formed on the substrate, and the first dielectric layer is used as a gate dielectric layer in the high-voltage circuit region. And then, forming a mask layer on the first dielectric layer, and patterning the mask layer, the first dielectric layer and the substrate to form a groove in the substrate. Then, an insulating layer is formed on the substrate to fill the trench. The mask layer and a part of the insulating layer are removed to expose the surface of the first dielectric layer. Then, the first dielectric layer in the low-voltage circuit region is removed to expose the surface of the substrate. Then, a second dielectric layer is formed on the substrate of the low-voltage circuit area, and the thickness of the second dielectric layer is smaller than that of the first dielectric layer.

Description

Fabrication method of gate dielectric layer

technical field

The invention relates to a method for manufacturing a semiconductor element, in particular to a method for manufacturing a gate dielectric layer.

Background technique

With the rapid development of the field of integrated circuits, high performance, high integration, low cost, light weight and short size have become the goals pursued by the design and manufacture of electronic products. For the current semiconductor industry, in order to meet the above goals, it is often necessary to manufacture components with multiple functions on the same chip.

Integrating high-voltage components and low-voltage components on the same chip is a way to achieve the above requirements. For example, use low-voltage components to manufacture control circuits, use high-voltage components to manufacture programmable read-only memory (Electrically Programmable Read-Only Memory; EPROM), flash memory (Flash Memory) or drive circuits for liquid crystal displays, etc.

However, in order to be able to withstand a higher breakdown voltage, the thickness of the gate oxide layer in high-voltage components often needs to be greater than 200 angstroms, which is much thicker than that of the gate oxide layer in low-voltage components. In this way, various difficulties will arise in the integration process of high-voltage components and low-voltage components.

FIG. 1A to FIG. 1F are cross-sectional views illustrating the manufacturing process of a conventional gate oxide layer. Referring to FIG. 1A , a pad oxide layer 110 and a mask layer 120 are formed on the common substrate 100 of the high voltage circuit area 101 and the low voltage circuit area 102 , and then the pad oxide layer 110 and the mask layer 120 are patterned.

Next, please refer to FIG. 1B , using the mask layer 120 as a mask, a trench 130 is etched in the substrate 100 . Then, a silicon oxide layer 140 is formed on the substrate 100 to fill the trench 130 and cover the substrate 100 . Afterwards, the silicon oxide layer 140 is removed until the mask layer 120 is exposed, and an active region 145 is defined at the same time.

Then, referring to FIG. 1C , a wet etching process is performed to remove the mask layer 120 and the pad oxide layer 110 . However, during the process of removing the mask layer 120 and the pad oxide layer 110 , the etchant used in the wet etching process will corrode the silicon oxide layer 140 , so that a divot 150 is formed at the corner of the trench 130 .

Then, referring to FIG. 1D , a thicker high voltage gate oxide layer 160 is formed on the substrate 100 . Due to the aforementioned formation of the cavity 150 , when the gate oxide layer 160 is formed, the cavity 150 around the corner of the STI structure will affect the oxidation rate. Therefore, the thickness of the high-voltage gate oxide layer 160 formed around the corners of the shallow trench isolation structure will be thinner than the thickness of the high-voltage gate oxide layer 160 formed in the active region 145, resulting in the problem of uneven thickness, that is, So-called gate oxide thinning. This phenomenon will cause electrical problems of the device and reduce the reliability of the gate oxide layer, which is undesirable in the semiconductor process.

After that, referring to FIG. 1E , a photoresist layer 165 is formed to cover the high voltage circuit region 101 , and the high voltage gate oxide layer 160 of the low voltage circuit region 102 is removed using the photoresist layer 165 as a mask. When removing the high-voltage gate oxide layer 160 of the low-voltage circuit region 102 , since the material of the silicon oxide layer 140 and the high-voltage gate oxide layer 160 are silicon oxide, the silicon oxide layer 140 is also etched. In this way, the shallow trench isolation structure (silicon oxide layer 140 ) in the low-voltage circuit region 102 produces a recess 168 .

Next, referring to FIG. 1F , the photoresist layer 165 is removed, and a thinner low-voltage gate oxide layer 170 is formed on the substrate 100 by thermal oxidation. Next, a doped polysilicon layer 180 is formed on the substrate 100 . After the doped polysilicon layer 180 is formed, parasitic transistors will be generated at the positions of the recesses 150 at the corners of the shallow trench isolation structure of the high voltage circuit region 101 , which will lead to electric leakage during normal operation of the memory. That is to say, the cavity 150 will accumulate charges, and then cause a sub-threshold leakage current of the device in the integrated circuit, thereby forming the so-called kink effect. The neck junction effect will reduce the quality of the device, reduce the stability and reliability of the device, and lead to a decrease in the yield of the process. In the low-voltage circuit region 102, due to the existence of the recess 168, the doped polysilicon will fill the region of the recess 168, and problems such as junction leakage (junction leakages) will occur, which will not only increase the power consumption, but also elongate the component. calculating speed.

Contents of the invention

In view of this, the object of the present invention is to provide a method for manufacturing a gate dielectric layer, which can avoid the thinning phenomenon of the gate dielectric layer at the corner of the shallow trench isolation structure, thereby improving the reliability and stability of the element .

Another object of the present invention is to provide a method for manufacturing a gate dielectric layer, which can solve the problem of the depression of the shallow trench isolation structure in the low-voltage circuit area, prevent the occurrence of junction leakage, and achieve the effects of low energy consumption and high-speed operation .

The invention provides a method for manufacturing a gate dielectric layer. This method, for example, provides a substrate, the substrate is at least divided into a high-voltage circuit area and a low-voltage circuit area, and a first dielectric layer is formed on the substrate, and the first dielectric layer is used as a gate oxide layer in the high-voltage circuit area. Afterwards, a mask layer is formed on the first dielectric layer, and the mask layer, the first dielectric layer and the substrate are patterned to form grooves in the substrate. Then, an insulating layer is formed on the substrate to fill up the trench. Next, part of the insulating layer and the mask layer are removed to expose the surface of the first dielectric layer. Then, the first dielectric layer and part of the insulating layer in the low-voltage circuit area are removed to expose the surface of the substrate. Next, a second dielectric layer is formed on the base of the low-voltage circuit area, and the thickness of the second dielectric layer is smaller than that of the first dielectric layer.

According to the method for manufacturing a gate dielectric layer in a preferred embodiment of the present invention, before forming the first dielectric layer, an RCA cleaning step is further included. The thickness of the first dielectric layer is, for example, between 200˜1000 angstroms, and the method of forming the first dielectric layer is, for example, a thermal oxidation method. The thickness of the second dielectric layer may be between 15-150 angstroms, and the method of forming the second dielectric layer is, for example, a thermal oxidation method.

According to the manufacturing method of the gate dielectric layer described in the preferred embodiment of the present invention, the method for removing the first dielectric layer in the low-voltage circuit region is, for example, forming a photoresist layer on the substrate of the high-voltage circuit region. Using the photoresist layer as a mask, etch the first dielectric layer in the low voltage circuit area. The photoresist layer is then removed. The method in which the first dielectric layer of the low-voltage circuit region is etched is, for example, a wet etching method.

According to the manufacturing method of the gate dielectric layer described in the preferred embodiment of the present invention, the above-mentioned method of patterning the mask layer, the first dielectric layer and the substrate to form trenches in the substrate is, for example: on the mask layer A patterned photoresist layer is formed, and the patterned photoresist layer is used as a mask to etch the mask layer, the first dielectric layer and the substrate to form grooves in the substrate. The patterned photoresist layer is then removed. The method of etching the mask layer, the first dielectric layer and the substrate is, for example, a dry etching method.

According to the manufacturing method of the gate dielectric layer described in the preferred embodiment of the present invention, after the step of forming the trench, a liner oxide layer may also be formed on the sidewall of the trench. The method of forming the liner oxide layer is, for example, thermal oxidation.

According to the manufacturing method of the gate dielectric layer described in the preferred embodiment of the present invention, the method for forming the insulating layer is, for example, a high-density plasma chemical vapor deposition method. If part of the insulating layer is beyond the surface of the mask layer, a chemical mechanical polishing process is also performed to remove the insulating layer on the mask layer with the mask layer as a stop layer. The etching process is, for example, an isotropic etching process.

The present invention is different from the existing method of first forming the pad oxide layer because the gate oxide layer of the high-voltage circuit region is first formed on the substrate. Therefore, the concave problem of the shallow trench isolation structure in the low-voltage circuit area can be solved, the occurrence of junction leakage can be prevented, and the effects of low energy consumption and high-speed operation can be achieved. In addition, when the liner oxide layer in the trench is formed, the bird's beak of silicon oxide is formed before the corner of the trench, which can avoid the thinning phenomenon of the gate dielectric layer at the corner of the shallow trench isolation structure, thereby improving the device performance. reliability and stability.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, the preferred embodiments are exemplified below and described in detail with accompanying drawings.

Description of drawings

1A to 1F are cross-sectional views illustrating the manufacturing process of a conventional gate oxide layer.

2A to 2F are cross-sectional views illustrating a manufacturing process of a gate dielectric layer according to a preferred embodiment of the present invention.

FIG. 3 is a partially enlarged view illustrating a cross-sectional view of a manufacturing process of a gate dielectric layer according to a preferred embodiment of the present invention shown in FIG. 2C .

simple notation

100, 200: base

101, 201: High voltage circuit area

102, 202: Low-voltage circuit area

110: pad oxide layer

120, 220: mask layer

130, 230: Groove

140: silicon oxide layer

145: Active area

150, 250: Dimple

160: High voltage gate oxide layer

165, 245: photoresist layer

168; concave

170: Low voltage gate oxide

180: doped polysilicon layer

210, 260: dielectric layer

225: Patterned photoresist layer

235: lining oxide layer

237: Beak

240: insulating layer

255: Shallow trench isolation structure

270: conductor layer

Detailed ways

2A to 2F are cross-sectional views illustrating a manufacturing process of a gate dielectric layer according to a preferred embodiment of the present invention.

Please refer to FIG. 2A , in this manufacturing method, for example, a substrate 200 is firstly provided, and the substrate 200 can be at least divided into a high-voltage circuit area 201 and a low-voltage circuit area 202 . A cleaning step is then performed on the substrate 200 with, for example, RCA solution (mixed solution of ammonia water NH ₄ OH and hydrogen peroxide H ₂ O ₂ ). Afterwards, a dielectric layer 210 is formed on the substrate 200 . The dielectric layer 210 is used as a gate dielectric layer in the high-voltage circuit region 201 , so the thickness of the dielectric layer 210 is thicker than the existing pad oxide layer, and the thickness of the dielectric layer 210 is about 200˜1000 angstroms. The forming method of the dielectric layer 210 is, for example, a thermal oxidation method.

After that, referring to FIG. 2B , a mask layer 220 is formed on the dielectric layer 210. The material of the mask layer 220 is, for example, silicon nitride, and its formation method is, for example, chemical vapor deposition. The thickness of the mask layer 220 is, for example, It is between 800-2000 Angstroms.

Next, a patterned photoresist layer 225 is formed on the mask layer 220 , and the patterned photoresist layer 225 is used as a mask to etch the mask layer 220 and the dielectric layer 210 . The material of the patterned photoresist layer 225 is, for example, a positive photoresist, and its formation method is, for example, to form a layer of photoresist material layer (not shown) on the mask layer 220 by spin coating. ), which is formed by developing the pattern after exposure. The method of etching the mask layer 220 and the dielectric layer 210 is, for example, a dry etching method.

Next, referring to FIG. 2C , the patterned photoresist layer 225 is removed. The method for removing the patterned photoresist layer 225 is, for example, dry stripping or wet stripping. Afterwards, the substrate 200 is etched using the mask layer 220 as a mask to form a trench 230 in the substrate 200 . The trench 230 is the trench in the subsequent shallow trench isolation structure. The method of etching the substrate 200 is, for example, a dry etching method. Then, to repair the lattice defects on the surface of the trench 230 caused by dry etching, a layer of liner oxide 235 is formed on the sidewall of the trench 230 . The formation method of the liner oxide layer 235 is, for example, a thermal oxidation method, and its thickness is, for example, about 80˜500 angstroms.

In FIG. 2C , when the liner oxide layer 235 is formed, a bird's beak 237 is formed at the corner of the trench. Please refer to FIG. 3 , which is an enlarged view of the bird's beak 237 . Since the formation of the bird's beak 237 increases the thickness of the silicon oxide at the corners, the thinning phenomenon of the gate oxide layer that occurs in the high-voltage circuit region can be avoided.

Next, referring to FIG. 2D , an insulating layer 240 is formed on the substrate 200 , the insulating layer 240 fills the trench 230 and covers the substrate 200 . The insulating layer 240 is used as an isolation structure in the subsequent shallow trench isolation structure. The material of the insulating layer 240 is, for example, silicon oxide or other suitable insulating materials, and its formation method is, for example, high-density plasma chemical vapor deposition. . The mask layer 220 is then removed to form the shallow trench isolation structure 255 . A method for removing the mask layer 220 is, for example, performing an isotropic etching process. Wherein, if part of the insulating layer 240 exceeds the surface of the mask layer 220, a chemical mechanical polishing process can be performed before removing the mask layer 220, and the mask layer 220 is used as a stop layer to remove the insulating layer on the mask layer 220. Layer 240.

In FIG. 2D, due to the isotropic etching process used to remove the mask layer 220, there will be an undercut phenomenon, so that a cavity 250 will occur between the insulating layer 240 and the dielectric layer 210, as in the prior art. The pocket 150 of 1C is normal. However, although the two may appear to be the same, they are actually quite different. Because the cavity 150 in FIG. 1C is adjacent to the substrate 100, a part of the substrate 100 is exposed, and the substrate 100 of this part will form a doped region (source/drain) subsequently; and in FIG. 2D of the present invention, because The dielectric layer 210 is thicker than conventional ones, so the cavity 250 is only in contact with the dielectric layer 210 and does not expose the substrate 200 . That is to say, the position of the cavity 250 is unlikely to form a so-called parasitic transistor, so the neck junction effect caused by the existing secondary enable current can be avoided, so the reliability and stability of the device can be improved, and the product reliability can be increased. Yield.

After that, referring to FIG. 2E , the dielectric layer 210 of the low voltage circuit area 202 is removed to expose the surface of the substrate 200 . The method of removing the dielectric layer 210 of the low-voltage circuit area 202 is, for example, to form a layer of photoresist layer 245 on the substrate 200 of the high-voltage circuit area 201, and then use the photoresist layer 245 as a mask to etch The dielectric layer 210 of the low voltage circuit area 202 . Wherein, the material of the photoresist layer 245 is, for example, a positive photoresist, and its formation method is, for example, to first form a layer of photoresist material layer (not shown) on the substrate 200 by spin coating, After the exposure, the pattern is developed to form a photoresist layer 245 . The method of etching the dielectric layer 210 of the low voltage circuit region 202 includes a wet etching method.

In the above embodiment, since the material of the insulating layer 240 is the same as that of the dielectric layer 210 , when the dielectric layer 210 of the low voltage circuit region 202 is removed, part of the insulating layer 240 is also removed. However, comparing FIG. 2E of the present invention with FIG. 1D in the prior art, it can be clearly seen that the manufacturing method of the gate dielectric layer disclosed in the present invention does not, as shown in FIG. 1D , in the low voltage circuit region 202, Form a depression. This is because a dielectric layer 210 has been formed on the substrate 200 in the present invention, and the thickness of the dielectric layer 210 is thicker than the existing pad oxide layer. Furthermore, the present invention does not need to remove the pad oxide layer first, and then remove the oxide layer in the low voltage circuit area after forming the oxide layer suitable for the high voltage circuit area as in the prior art. Therefore, when the present invention removes the dielectric layer 210 on the low-voltage circuit region 202, it will not cause the insulating layer 240 in the isolation structure to have a concave phenomenon, thereby preventing the occurrence of junction leakage and reducing Component operation energy consumption, the effect of speeding up the operation speed.

Then, referring to FIG. 2F , the photoresist layer 245 on the high voltage circuit area 201 is removed, such as by wet stripping or dry stripping. Next, a dielectric layer 260 is formed on the substrate 200, and the dielectric layer 260 is formed by thermal oxidation, for example. The thickness of the dielectric layer 260 is smaller than that of the dielectric layer 210 , and the thickness of the dielectric layer 260 is, for example, between 15˜150 angstroms. In addition, the method for forming the dielectric layer 260 may also be to retain the photoresist layer 245 on the high voltage circuit region 201 first, and directly form the dielectric layer 260 on the substrate 200 by chemical vapor deposition. The photoresist layer 245 is then removed.

Next, please continue to refer to FIG. 2F , a conductive layer 270 is formed on the dielectric layer 260 and the dielectric layer 210 . The material of the conductive layer 270 is, for example, doped polysilicon, and its formation method is, for example, to first form a layer of undoped polysilicon layer (not shown) by chemical vapor deposition, and then form it by ion implantation. Of course, it can also be formed by using The doped polysilicon layer is formed by chemical vapor deposition in the way of on-site implantation. As for the subsequent process, it varies depending on the device to be formed, and should be well known to those skilled in the art, and will not be repeated here.

To sum up, the present invention directly forms the gate oxide layer of the high-voltage circuit region on the substrate, instead of forming the pad oxide layer first and then removing the pad oxide layer as in the prior art. Not only are the process steps relatively simple, which can save cost and process time, but also can solve the problem of the recess of the shallow trench isolation structure in the low-voltage circuit area, prevent the occurrence of junction leakage, and achieve low energy consumption, high-speed computing and other effects. In addition, when the liner oxide layer in the trench is formed, the bird's beak of silicon oxide is formed before the corner of the trench, which can avoid the thinning phenomenon of the gate dielectric layer at the corner of the shallow trench isolation structure, and improve the device performance. reliability and stability.

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention It shall prevail as defined in the appended claims.

Claims (15)

1, a kind of manufacture method of gate dielectric layer comprises:

One substrate is provided, and a high voltage circuit area and a low-voltage circuit district are divided in this substrate at least;

Form one first dielectric layer in this substrate, this first dielectric layer is as the usefulness of the gate dielectric layer in this high voltage circuit area;

On this first dielectric layer, form a mask layer;

This mask layer of patterning, this first dielectric layer and this substrate are to form a groove in this substrate;

In this substrate, form an insulating barrier to fill up this groove;

Remove this mask layer, expose the surface of this first dielectric layer;

Remove this first dielectric layer in this low-voltage circuit district, expose the surface of this substrate; And

Form one second dielectric layer in this substrate in this low-voltage circuit district, the thickness of this second dielectric layer is less than the thickness of this first dielectric layer.

2, the manufacture method of gate dielectric layer as claimed in claim 1, wherein the thickness of this first dielectric layer is between 200～1000 dusts.

3, the manufacture method of gate dielectric layer as claimed in claim 1, the method that wherein forms this first dielectric layer comprises thermal oxidation method.

4, the manufacture method of gate dielectric layer as claimed in claim 1 wherein removes the method for this first dielectric layer in this low-voltage circuit district, comprising:

In this substrate of this high voltage circuit area, form a photoresist layer;

With this photoresist layer is mask, this first dielectric layer in this low-voltage circuit district of etching; And

Remove this photoresist layer.

5, the manufacture method of gate dielectric layer as claimed in claim 4, wherein the method for this first dielectric layer in this low-voltage circuit district of etching comprises wet etching.

6, the manufacture method of gate dielectric layer as claimed in claim 1, wherein this mask layer of patterning, this first dielectric layer and this substrate comprises with the method that forms this groove in this substrate:

On this mask layer, form a patterning photoresist layer;

With this patterning photoresist layer is mask, and this mask layer of etching, this first dielectric layer and this substrate are to form this groove in this substrate; And

Remove this patterning photoresist layer.

7, the manufacture method of gate dielectric layer as claimed in claim 6, wherein the method for this mask layer of etching, this first dielectric layer and this substrate comprises the dry-etching method.

8, the manufacture method of gate dielectric layer as claimed in claim 1, wherein after the step that forms this groove, the sidewall that also is included in this groove forms a lining oxide layer.

9, the manufacture method of gate dielectric layer as claimed in claim 8, the method that wherein forms this lining oxide layer comprises thermal oxidation method.

10, the manufacture method of gate dielectric layer as claimed in claim 1 wherein if this insulating barrier of part exceeds this mask layer surface, also comprises:

Carrying out a chemical mechanical milling tech, is that stop layer removes this insulating barrier on this mask layer with this mask layer.

11, the manufacture method of gate dielectric layer as claimed in claim 10, wherein this etch process comprises isotropic etching.

12, the manufacture method of gate dielectric layer as claimed in claim 1, the method that wherein forms this insulating barrier comprises the high density plasma CVD method.

13, the manufacture method of gate dielectric layer as claimed in claim 1 wherein forms before this first dielectric layer, also comprises carrying out a RCA cleaning step.

14, the manufacture method of gate dielectric layer as claimed in claim 1, wherein the thickness of this second dielectric layer is between 15～150 dusts.

15, the manufacture method of gate dielectric layer as claimed in claim 1, the method that wherein forms this second dielectric layer comprises thermal oxidation method.

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