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CN114242658B - Process Integration Method for Integrating High Voltage CMOS into Logic Process - Google Patents

Process Integration Method for Integrating High Voltage CMOS into Logic Process Download PDF

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CN114242658B
CN114242658B CN202111472335.XA CN202111472335A CN114242658B CN 114242658 B CN114242658 B CN 114242658B CN 202111472335 A CN202111472335 A CN 202111472335A CN 114242658 B CN114242658 B CN 114242658B
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CN114242658A (en
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钱文生
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181Manufacturing their gate insulating layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188Manufacturing their isolation regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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Abstract

本发明公开了一种在逻辑工艺中集成高压CMOS的工艺集成方法,包括:步骤一、形成高压CMOS的第一沟道区;步骤二、形成高压CMOS的第一漂移区;步骤三、进行第一次炉管热推阱;步骤四、采用第一次热氧化工艺形成高压栅氧化层;步骤五、形成浅沟槽隔离,位于高压CMOS的形成区域的第一浅沟槽隔离的深度小于位于逻辑器件的形成区域中的第二浅沟槽隔离的深度;步骤六、在逻辑器件的形成区域中完成栅极导电材料层的形成工艺之前的工艺,之后形成栅极导电材料层;步骤七、进行第一导电类型重掺杂的源漏注入。本发明能消除高压CMOS所需要的热过程对有源区产生的应力并从而消除由应力产生的有源区缺陷,提高高压栅氧化层的质量和高压CMOS的性能。

The present invention discloses a process integration method for integrating high-voltage CMOS in a logic process, comprising: step 1, forming a first channel region of the high-voltage CMOS; step 2, forming a first drift region of the high-voltage CMOS; step 3, performing a first furnace tube thermal push well; step 4, using a first thermal oxidation process to form a high-voltage gate oxide layer; step 5, forming a shallow trench isolation, wherein the depth of the first shallow trench isolation located in the formation region of the high-voltage CMOS is less than the depth of the second shallow trench isolation located in the formation region of the logic device; step 6, completing the process before the formation process of the gate conductive material layer in the formation region of the logic device, and then forming the gate conductive material layer; step 7, performing a heavily doped source-drain injection of the first conductive type. The present invention can eliminate the stress generated by the thermal process required by the high-voltage CMOS on the active region and thereby eliminate the active region defects generated by the stress, thereby improving the quality of the high-voltage gate oxide layer and the performance of the high-voltage CMOS.

Description

在逻辑工艺中集成高压CMOS的工艺集成方法Process Integration Method for Integrating High Voltage CMOS into Logic Process

技术领域Technical Field

本发明涉及一种半导体集成电路制造方法,特别涉及一种在逻辑工艺中集成高压CMOS的工艺集成方法。The invention relates to a semiconductor integrated circuit manufacturing method, in particular to a process integration method for integrating high-voltage CMOS in a logic process.

背景技术Background Art

高压CMOS技术是屏幕显示驱动芯片的制作工艺。其特点是,高压CMOS器件需要与逻辑工艺集成,以实现高压驱动和逻辑信号处理的有机结合。High-voltage CMOS technology is the manufacturing process of screen display driver chips. Its characteristic is that high-voltage CMOS devices need to be integrated with logic processes to achieve an organic combination of high-voltage drive and logic signal processing.

高压CMOS器件的栅极和漏极都需要承受高压,因此需要有厚栅氧化层即厚栅氧化硅介质层,也需要有经过热推阱形成较均匀掺杂的漏端漂移区,这些都需要在工艺中引入大量的热过程。虽然这些热过程在逻辑器件制作前完成,但如果热过程发生在逻辑工艺的浅沟槽隔离(STI)之后,就会在有源区形成较大应力,引起有源区的缺陷和位错,造成器件的失效。The gate and drain of high-voltage CMOS devices need to withstand high voltage, so a thick gate oxide layer, i.e. a thick gate oxide silicon dielectric layer, is required, and a drain drift region with relatively uniform doping is also required after thermal well pushing, which requires the introduction of a large number of thermal processes in the process. Although these thermal processes are completed before the logic device is manufactured, if the thermal process occurs after the shallow trench isolation (STI) of the logic process, a large stress will be formed in the active area, causing defects and dislocations in the active area, resulting in device failure.

高压CMOS的厚栅氧化硅的氧化工艺如果在STI之后完成,在STI的边缘区氧化速度偏慢,造成高压CMOS的栅氧化层厚度不均匀,在Id-Vg曲线中有双峰出现,形成器件的高漏电流现象,Id为漏极电流,Vg为栅极电压。If the oxidation process of the thick gate silicon oxide of the high-voltage CMOS is completed after STI, the oxidation speed in the edge area of the STI will be slow, resulting in uneven thickness of the gate oxide layer of the high-voltage CMOS, double peaks in the Id-Vg curve, and high leakage current of the device. Id is the drain current and Vg is the gate voltage.

高压CMOS的低导通电阻要求其漂移区的STI的深度不宜太深,与先进逻辑工艺的STI深度不兼容。The low on-resistance of high-voltage CMOS requires that the depth of the STI in the drift region should not be too deep, which is incompatible with the STI depth of advanced logic processes.

发明内容Summary of the invention

本发明所要解决的技术问题是提供一种在逻辑工艺中集成高压CMOS的工艺集成方法,能消除高压CMOS所需要的热过程对有源区产生的应力并从而消除由应力产生的有源区缺陷,还能同时提高CMOS的性能。The technical problem to be solved by the present invention is to provide a process integration method for integrating high-voltage CMOS in a logic process, which can eliminate the stress generated by the thermal process required by the high-voltage CMOS on the active area and thereby eliminate the active area defects caused by the stress, and can also improve the performance of the CMOS at the same time.

为解决上述技术问题,本发明提供的在逻辑工艺中集成高压CMOS的工艺集成方法中逻辑器件的工作电压小于高压CMOS的工作电压,包括如下步骤:In order to solve the above technical problems, the present invention provides a process integration method for integrating high-voltage CMOS in a logic process, wherein the operating voltage of the logic device is lower than the operating voltage of the high-voltage CMOS, and comprises the following steps:

步骤一、在所述高压CMOS的形成区域的选定区域的半导体衬底中形成第二导电类型掺杂的第一沟道区。Step 1: forming a first channel region doped with a second conductivity type in a semiconductor substrate in a selected region of the high voltage CMOS formation region.

步骤二、在所述高压CMOS的形成区域的选定区域的所述半导体衬底中形成第一导电类型掺杂的第一漂移区。Step 2: forming a first drift region doped with a first conductivity type in the semiconductor substrate in a selected region of the high voltage CMOS formation region.

步骤三、进行第一次炉管热推阱,所述炉管热推阱具有第一热过程,所述第一热过程越多所述第一漂移区的掺杂均匀性越好,所述第一热过程增加到使所述第一漂移区的掺杂均匀性提高到满足所述高压CMOS的耐压要求。Step 3: performing the first furnace tube thermal push well, wherein the furnace tube thermal push well has a first thermal process, the more the first thermal processes are performed, the better the doping uniformity of the first drift region is, and the first thermal processes are increased until the doping uniformity of the first drift region is improved to meet the withstand voltage requirement of the high-voltage CMOS.

步骤四、采用第一次热氧化工艺在所述高压CMOS的形成区域的所述半导体衬底表面形成高压栅氧化层,所述第一次热氧化工艺具有第二热过程,所述第二热过程越多,所述高压栅氧化层的厚度越厚,所述第二热过程增加到使所述高压栅氧化层满足所述高压CMOS的耐压要求。Step 4: A first thermal oxidation process is used to form a high-voltage gate oxide layer on the surface of the semiconductor substrate in the formation area of the high-voltage CMOS. The first thermal oxidation process has a second thermal process. The more the second thermal process is, the thicker the high-voltage gate oxide layer is. The second thermal process is increased to make the high-voltage gate oxide layer meet the voltage resistance requirements of the high-voltage CMOS.

步骤五、形成浅沟槽隔离,所述浅沟槽隔离包括位于所述高压CMOS的形成区域的第一浅沟槽隔离和位于所述逻辑器件的形成区域中的第二浅沟槽隔离,利用形成所述浅沟槽隔离之前在所述高压CMOS的形成区域中形成有所述高压栅氧化层的特点,使所述第一浅沟槽隔离的深度小于所述第二浅沟槽隔离的深度。Step five, forming shallow trench isolation, the shallow trench isolation includes a first shallow trench isolation located in the formation area of the high-voltage CMOS and a second shallow trench isolation located in the formation area of the logic device, and utilizing the characteristic that the high-voltage gate oxide layer is formed in the formation area of the high-voltage CMOS before forming the shallow trench isolation, so that the depth of the first shallow trench isolation is smaller than the depth of the second shallow trench isolation.

所述浅沟槽隔离所围区域的所述半导体衬底作为有源区,利用所述第一热过程和所述第二热过程都位于所述浅沟槽隔离形成工艺之前的特点,减少所述有源区所受到的应力并消除由于应力所产生的有源区缺陷。The semiconductor substrate in the area surrounded by the shallow trench isolation is used as an active area. The stress on the active area is reduced and active area defects caused by stress are eliminated by utilizing the characteristics that the first thermal process and the second thermal process are both located before the shallow trench isolation formation process.

所述第一次热氧化工艺放置在所述浅沟槽隔离的形成工艺之前则保证所述高压栅氧化层的厚度不会受到所述浅沟槽隔离的边缘影响,从而提升所述高压栅氧化层的均匀性。Placing the first thermal oxidation process before the shallow trench isolation forming process ensures that the thickness of the high-voltage gate oxide layer will not be affected by the edge of the shallow trench isolation, thereby improving the uniformity of the high-voltage gate oxide layer.

步骤六、在所述逻辑器件的形成区域中完成栅极导电材料层的形成工艺之前的工艺,之后,同时在所述高压CMOS的形成区域和所述逻辑器件的形成区域中形成栅极导电材料层。Step six: completing the processes before the gate conductive material layer formation process in the formation region of the logic device, and then simultaneously forming the gate conductive material layer in the formation region of the high-voltage CMOS and the formation region of the logic device.

步骤七、进行第一导电类型重掺杂的源漏注入同时在所述高压CMOS的形成区域和所述逻辑器件的形成区域形成源漏区。Step seven: performing heavily doped source and drain implantation of the first conductivity type to simultaneously form source and drain regions in the high voltage CMOS formation region and the logic device formation region.

进一步的改进是,所述逻辑器件包括中压CMOS和低压CMOS,所述中压CMOS的工作电压小于高压CMOS的工作电压以及所述中压CMOS的工作电压大于低压CMOS的工作电压。A further improvement is that the logic device includes a medium voltage CMOS and a low voltage CMOS, the working voltage of the medium voltage CMOS is lower than the working voltage of the high voltage CMOS and the working voltage of the medium voltage CMOS is higher than the working voltage of the low voltage CMOS.

进一步的改进是,所述中压CMOS的中压栅氧化层采用第二次热氧化工艺形成,且所述第二次热氧化工艺放置在步骤四的所述第一次热氧化工艺之后以及步骤五的所述浅沟槽隔离形成工艺之前;所述中压栅氧化层的厚度薄于所述高压栅氧化层的厚度。A further improvement is that the medium-voltage gate oxide layer of the medium-voltage CMOS is formed by a second thermal oxidation process, and the second thermal oxidation process is placed after the first thermal oxidation process in step four and before the shallow trench isolation formation process in step five; the thickness of the medium-voltage gate oxide layer is thinner than the thickness of the high-voltage gate oxide layer.

所述第二次热氧化工艺具有第三热过程,利用所述第三热过程位于所述浅沟槽隔离形成工艺之前的特点,减少所述有源区所受到的应力并消除由于应力所产生的有源区缺陷。The second thermal oxidation process has a third thermal process. The third thermal process is performed before the shallow trench isolation formation process to reduce the stress on the active area and eliminate the defects in the active area caused by the stress.

同时利用所述第二次热氧化工艺放置在所述浅沟槽隔离的形成工艺之前来保证所述中压栅氧化层的厚度不会受到所述浅沟槽隔离的边缘影响,从而提升所述中压栅氧化层的均匀性。At the same time, the second thermal oxidation process is placed before the shallow trench isolation forming process to ensure that the thickness of the medium voltage gate oxide layer will not be affected by the edge of the shallow trench isolation, thereby improving the uniformity of the medium voltage gate oxide layer.

进一步的改进是,步骤六包括如下分步骤:A further improvement is that step six includes the following sub-steps:

步骤61、在所述中压CMOS的形成区域中形成所述中压CMOS的具有第二导电类型掺杂的第二沟道区。Step 61 : forming a second channel region of the medium voltage CMOS doped with a second conductivity type in a formation region of the medium voltage CMOS.

步骤62、在所述低压CMOS的形成区域中形成所述低压CMOS的具有第二导电类型掺杂的第三沟道区。Step 62 : forming a third channel region of the low voltage CMOS doped with the second conductivity type in the formation region of the low voltage CMOS.

步骤63、去除所述低压CMOS的形成区域中的所述中压栅氧化层。Step 63: removing the medium voltage gate oxide layer in the low voltage CMOS formation area.

步骤64、进行第三次热氧化工艺在所述低压CMOS的形成区域的所述半导体衬底表面形成低压栅氧化层。Step 64 , performing a third thermal oxidation process to form a low-voltage gate oxide layer on the surface of the semiconductor substrate in the formation area of the low-voltage CMOS.

步骤65、形成所述栅极导电材料层并对所述栅极导电材料层进行图形化刻蚀,将图形化后的所述栅极导电材料层所覆盖区域外的所述高压栅氧化层、所述中压栅氧化层和所述低压栅氧化层去除。Step 65 , forming the gate conductive material layer and performing patterning etching on the gate conductive material layer, and removing the high voltage gate oxide layer, the medium voltage gate oxide layer and the low voltage gate oxide layer outside the area covered by the patterned gate conductive material layer.

进一步的改进是,所述栅极导电材料层采用多晶硅栅。A further improvement is that the gate conductive material layer is made of polysilicon gate.

进一步的改进是,所述半导体衬底包括硅衬底。A further improvement is that the semiconductor substrate comprises a silicon substrate.

进一步的改进是,所述高压CMOS包括高压NMOS和高压PMOS。A further improvement is that the high-voltage CMOS includes a high-voltage NMOS and a high-voltage PMOS.

对于所述高压NMOS,第一导电类型为N型,第二导电类型为P型。For the high-voltage NMOS, the first conductivity type is N-type, and the second conductivity type is P-type.

对于所述高压PMOS,第一导电类型为P型,第二导电类型为N型。For the high-voltage PMOS, the first conductivity type is P-type, and the second conductivity type is N-type.

进一步的改进是,步骤一中,所述高压NMOS的所述第一沟道区和所述高压PMOS的所述第一沟道区分开进行。A further improvement is that, in step 1, the first channel region of the high voltage NMOS and the first channel region of the high voltage PMOS are performed separately.

步骤二中,所述高压NMOS的所述第一漂移区和所述高压PMOS的所述第一漂移区分开进行。In step 2, the first drift region of the high voltage NMOS and the first drift region of the high voltage PMOS are performed separately.

进一步的改进是,步骤三和步骤四中,所述高压NMOS和所述高压PMOS的形成区域的工艺同时进行。A further improvement is that in step three and step four, the processes for forming the high voltage NMOS and the high voltage PMOS regions are performed simultaneously.

进一步的改进是,所述中压CMOS包括中压NMOS和中压PMOS;A further improvement is that the medium voltage CMOS includes a medium voltage NMOS and a medium voltage PMOS;

对于所述中压NMOS,第一导电类型为N型,第二导电类型为P型;For the medium voltage NMOS, the first conductivity type is N type, and the second conductivity type is P type;

对于所述中压PMOS,第一导电类型为P型,第二导电类型为N型。For the medium voltage PMOS, the first conductivity type is P type, and the second conductivity type is N type.

进一步的改进是,步骤61中,所述中压NMOS的所述第二沟道区和所述中压PMOS的所述第二沟道区分开进行。A further improvement is that, in step 61, the second channel region of the medium voltage NMOS and the second channel region of the medium voltage PMOS are performed separately.

进一步的改进是,所述低压CMOS包括低压NMOS和低压PMOS;A further improvement is that the low voltage CMOS includes a low voltage NMOS and a low voltage PMOS;

对于所述低压NMOS,第一导电类型为N型,第二导电类型为P型;For the low voltage NMOS, the first conductivity type is N type, and the second conductivity type is P type;

对于所述低压PMOS,第一导电类型为P型,第二导电类型为N型。For the low voltage PMOS, the first conductivity type is P type, and the second conductivity type is N type.

进一步的改进是,步骤62中,所述低压NMOS的所述第三沟道区和所述低压PMOS的所述第三沟道区分开进行。A further improvement is that, in step 62, the third channel region of the low voltage NMOS and the third channel region of the low voltage PMOS are processed separately.

进一步的改进是,步骤64中,所述低压NMOS和所述低压PMOS的形成区域的工艺同时进行。A further improvement is that, in step 64, the processes for forming the low voltage NMOS and the low voltage PMOS regions are performed simultaneously.

进一步的改进是,屏幕显示驱动芯片中采用所述高压CMOS。A further improvement is that the high voltage CMOS is used in the screen display driver chip.

本发明对逻辑器件和高压CMOS的集成工艺中的工艺顺序做了特别的设置,将高压CMOS中为满足高压CMOS的耐压性能而必须采用的热过程即第一热过程和第二热过程都放置在浅沟槽隔离的形成工艺之前,这样就能避免在第一热过程和第二热过程中会出现有源区和浅沟槽隔离的不同材料的热膨胀系数不同而出现的应力,从而能消除有源区受到应力作用而产生缺陷和位错。The present invention makes a special arrangement for the process sequence in the integration process of the logic device and the high-voltage CMOS, and places the thermal processes that must be used in the high-voltage CMOS to meet the voltage resistance performance of the high-voltage CMOS, namely the first thermal process and the second thermal process, before the shallow trench isolation formation process, so that the stress caused by the different thermal expansion coefficients of different materials in the active area and the shallow trench isolation in the first thermal process and the second thermal process can be avoided, thereby eliminating the defects and dislocations caused by the stress in the active area.

同时,本发明高压CMOS所需要的热过程如第一热过程和第二热过程由于不会受到对有源区产生不利影响的限制,故第一热过程和第二热过程都能充分进行,从而能使得第一漂移区的掺杂均匀性得到充分提升,高压栅氧化层的厚度也能增加到耐压要求值,最后能提升高压CMOS的耐压性能。At the same time, the thermal processes required by the high-voltage CMOS of the present invention, such as the first thermal process and the second thermal process, are not restricted by the adverse effects on the active region, so the first thermal process and the second thermal process can be fully carried out, so that the doping uniformity of the first drift region can be fully improved, and the thickness of the high-voltage gate oxide layer can also be increased to the withstand voltage requirement value, and finally the withstand voltage performance of the high-voltage CMOS can be improved.

另外,本发明的第一次热氧化工艺由于放置在浅沟槽隔离形成之前,能防止出现浅沟槽隔离边缘对高压栅氧化层的厚度降低的情形,最后能使高压栅氧化层在各区域的厚度均匀,从而能提升高压栅氧化层的质量。In addition, since the first thermal oxidation process of the present invention is placed before the shallow trench isolation is formed, it can prevent the shallow trench isolation edge from reducing the thickness of the high-voltage gate oxide layer. Finally, the thickness of the high-voltage gate oxide layer can be made uniform in each area, thereby improving the quality of the high-voltage gate oxide layer.

另外,本发明的高压栅氧化层形成在浅沟槽隔离之前,这样在浅沟槽隔离形成过程中,采用相同的刻蚀工艺形成浅沟槽时,形成有高压栅氧化层的区域和未形成高压栅氧化层的区域会得到不同的浅沟槽深度,且高压栅氧化层的区域的浅沟槽的深度会更浅,所以高压CMOS的浅沟槽隔离即第一浅沟槽隔离的深度会更浅,这和高压CMOS对设置在漂移区中的第一浅沟槽隔离的深度要求相符合,因为这有利于降低导通电阻,故本发明能节省制造不同深度的浅沟槽隔离的工艺成本。In addition, the high-voltage gate oxide layer of the present invention is formed before the shallow trench isolation. In this way, during the shallow trench isolation formation process, when the shallow trench is formed using the same etching process, the area where the high-voltage gate oxide layer is formed and the area where the high-voltage gate oxide layer is not formed will obtain different shallow trench depths, and the depth of the shallow trench in the area of the high-voltage gate oxide layer will be shallower, so the depth of the shallow trench isolation of the high-voltage CMOS, that is, the first shallow trench isolation, will be shallower, which is consistent with the depth requirement of the high-voltage CMOS for the first shallow trench isolation set in the drift region. Because this is conducive to reducing the on-resistance, the present invention can save the process cost of manufacturing shallow trench isolations of different depths.

附图说明BRIEF DESCRIPTION OF THE DRAWINGS

下面结合附图和具体实施方式对本发明作进一步详细的说明:The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

图1是本发明实施例在逻辑工艺中集成高压CMOS的工艺集成方法的流程图;1 is a flow chart of a process integration method for integrating high voltage CMOS in a logic process according to an embodiment of the present invention;

图2A-图2N是本发明实施例在逻辑工艺中集成高压CMOS的工艺集成方法各步骤中的器件结构示意图。2A-2N are schematic diagrams of device structures in various steps of a process integration method for integrating high-voltage CMOS in a logic process according to an embodiment of the present invention.

具体实施方式DETAILED DESCRIPTION

如图1所示,是本发明实施例在逻辑工艺中集成高压CMOS的工艺集成方法的流程图;如图2A至图2N所示,是本发明实施例在逻辑工艺中集成高压CMOS的工艺集成方法各步骤中的器件结构示意图;本发明实施例在逻辑工艺中集成高压CMOS的工艺集成方法中逻辑器件的工作电压小于高压CMOS的工作电压,包括如下步骤:As shown in FIG. 1 , it is a flow chart of a process integration method for integrating high-voltage CMOS in a logic process according to an embodiment of the present invention; as shown in FIG. 2A to FIG. 2N , it is a schematic diagram of a device structure in each step of a process integration method for integrating high-voltage CMOS in a logic process according to an embodiment of the present invention; in the process integration method for integrating high-voltage CMOS in a logic process according to an embodiment of the present invention, the operating voltage of the logic device is lower than the operating voltage of the high-voltage CMOS, and includes the following steps:

步骤一、如图2A所示,在所述高压CMOS的形成区域201的选定区域的半导体衬底101中形成第二导电类型掺杂的第一沟道区102。所述高压CMOS的形成区域201在图2C中用大括号标出。Step 1: As shown in Fig. 2A, a first channel region 102 doped with a second conductivity type is formed in a semiconductor substrate 101 in a selected region of the high voltage CMOS formation region 201. The high voltage CMOS formation region 201 is marked with curly brackets in Fig. 2C.

本发明实施例中,所述半导体衬底101包括硅衬底。In the embodiment of the present invention, the semiconductor substrate 101 includes a silicon substrate.

步骤二、如图2B所示,在所述高压CMOS的形成区域201的选定区域的所述半导体衬底101中形成第一导电类型掺杂的第一漂移区103。Step 2: As shown in FIG. 2B , a first drift region 103 doped with a first conductivity type is formed in the semiconductor substrate 101 in a selected region of the high voltage CMOS formation region 201 .

步骤三、如图2B所示,进行第一次炉管热推阱,所述炉管热推阱具有第一热过程,所述第一热过程越多所述第一漂移区103的掺杂均匀性越好,所述第一热过程增加到使所述第一漂移区103的掺杂均匀性提高到满足所述高压CMOS的耐压要求。Step three, as shown in FIG2B , the first furnace tube thermal push well is performed, and the furnace tube thermal push well has a first thermal process. The more the first thermal processes are performed, the better the doping uniformity of the first drift region 103 is. The first thermal processes are increased until the doping uniformity of the first drift region 103 is improved to meet the withstand voltage requirement of the high-voltage CMOS.

步骤四、如图2D所示,采用第一次热氧化工艺在所述高压CMOS的形成区域201的所述半导体衬底101表面形成高压栅氧化层104a,所述第一次热氧化工艺具有第二热过程,所述第二热过程越多,所述高压栅氧化层104a的厚度越厚,所述第二热过程增加到使所述高压栅氧化层104a满足所述高压CMOS的耐压要求。Step 4, as shown in Figure 2D, a first thermal oxidation process is used to form a high-voltage gate oxide layer 104a on the surface of the semiconductor substrate 101 in the formation area 201 of the high-voltage CMOS. The first thermal oxidation process has a second thermal process. The more the second thermal process is performed, the thicker the high-voltage gate oxide layer 104a is. The second thermal process is increased to make the high-voltage gate oxide layer 104a meet the voltage resistance requirements of the high-voltage CMOS.

如图2C所示,在进行所述第一次热氧化工艺之前,还包括形成第一硬质掩膜层103并对所述第一硬质掩膜层103进行图形化的步骤,图形化后的所述第一硬质掩膜层103将所述高压CMOS的形成区域201打开。As shown in FIG. 2C , before the first thermal oxidation process is performed, a step of forming a first hard mask layer 103 and patterning the first hard mask layer 103 is also included. The patterned first hard mask layer 103 opens the high-voltage CMOS formation area 201 .

本发明实施例中,所述逻辑器件包括中压CMOS和低压CMOS,所述中压CMOS的工作电压小于高压CMOS的工作电压以及所述中压CMOS的工作电压大于低压CMOS的工作电压。In an embodiment of the present invention, the logic device includes a medium voltage CMOS and a low voltage CMOS, the operating voltage of the medium voltage CMOS is lower than the operating voltage of the high voltage CMOS and the operating voltage of the medium voltage CMOS is higher than the operating voltage of the low voltage CMOS.

如图2E所示,所述中压CMOS的中压栅氧化层104b采用第二次热氧化工艺形成,且所述第二次热氧化工艺放置在所述第一次热氧化工艺之后以及后续步骤五的所述浅沟槽隔离形成工艺之前;所述中压栅氧化层104b的厚度薄于所述高压栅氧化层104a的厚度。As shown in Figure 2E, the medium-voltage gate oxide layer 104b of the medium-voltage CMOS is formed by a second thermal oxidation process, and the second thermal oxidation process is placed after the first thermal oxidation process and before the shallow trench isolation formation process in the subsequent step five; the thickness of the medium-voltage gate oxide layer 104b is thinner than the thickness of the high-voltage gate oxide layer 104a.

所述第二次热氧化工艺具有第三热过程。The second thermal oxidation process has a third thermal process.

步骤五、如图2I所示,形成浅沟槽隔离,所述浅沟槽隔离包括位于所述高压CMOS的形成区域201的第一浅沟槽隔离106a和位于所述逻辑器件的形成区域中的第二浅沟槽隔离106b,利用形成所述浅沟槽隔离之前在所述高压CMOS的形成区域201中形成有所述高压栅氧化层104a的特点,使所述第一浅沟槽隔离106a的深度小于所述第二浅沟槽隔离106b的深度。Step five, as shown in FIG. 2I , a shallow trench isolation is formed, wherein the shallow trench isolation includes a first shallow trench isolation 106a located in the formation area 201 of the high-voltage CMOS and a second shallow trench isolation 106b located in the formation area of the logic device. By utilizing the characteristic that the high-voltage gate oxide layer 104a is formed in the formation area 201 of the high-voltage CMOS before forming the shallow trench isolation, the depth of the first shallow trench isolation 106a is smaller than the depth of the second shallow trench isolation 106b.

所述浅沟槽隔离所围区域的所述半导体衬底101作为有源区,利用所述第一热过程和所述第二热过程都位于所述浅沟槽隔离形成工艺之前的特点,减少所述有源区所受到的应力并消除由于应力所产生的有源区缺陷。同时,本发明实施例中,还利用所述第三热过程位于所述浅沟槽隔离形成工艺之前的特点,进一步减少所述有源区所受到的应力并消除由于应力所产生的有源区缺陷。The semiconductor substrate 101 in the area surrounded by the shallow trench isolation is used as an active area, and the first thermal process and the second thermal process are both located before the shallow trench isolation formation process to reduce the stress on the active area and eliminate the active area defects caused by the stress. At the same time, in the embodiment of the present invention, the third thermal process is also located before the shallow trench isolation formation process to further reduce the stress on the active area and eliminate the active area defects caused by the stress.

所述第一次热氧化工艺放置在所述浅沟槽隔离的形成工艺之前则保证所述高压栅氧化层104a的厚度不会受到所述浅沟槽隔离的边缘影响,从而提升所述高压栅氧化层104a的均匀性。同样,本发明实施例中,利用所述第二次热氧化工艺放置在所述浅沟槽隔离的形成工艺之前来保证所述中压栅氧化层104b的厚度不会受到所述浅沟槽隔离的边缘影响,从而提升所述中压栅氧化层104b的均匀性。The first thermal oxidation process is placed before the shallow trench isolation formation process to ensure that the thickness of the high-voltage gate oxide layer 104a will not be affected by the edge of the shallow trench isolation, thereby improving the uniformity of the high-voltage gate oxide layer 104a. Similarly, in the embodiment of the present invention, the second thermal oxidation process is placed before the shallow trench isolation formation process to ensure that the thickness of the medium-voltage gate oxide layer 104b will not be affected by the edge of the shallow trench isolation, thereby improving the uniformity of the medium-voltage gate oxide layer 104b.

本发明实施例中,形成浅沟槽隔离的步骤包括如下分步骤:In an embodiment of the present invention, the step of forming shallow trench isolation includes the following sub-steps:

如图2F所示,形成第二硬质掩膜层302。第二硬质掩膜层302通常采用氮化硅,而所述高压栅氧化层104a和所述中压栅氧化层104b则作为所述第二硬质掩膜层302的氮化硅和所述半导体衬底101之间的缓冲层。2F , a second hard mask layer 302 is formed. The second hard mask layer 302 is usually made of silicon nitride, and the high voltage gate oxide layer 104a and the medium voltage gate oxide layer 104b serve as buffer layers between the silicon nitride of the second hard mask layer 302 and the semiconductor substrate 101 .

如图2G所示,对所述第二硬质掩膜层302进行图形化刻蚀。通常包括,采用光刻工艺定义出所述浅沟槽隔离的形成区域,之后根据光刻定义对所述第二硬质掩膜层302进行刻蚀将所述浅沟槽隔离的形成区域打开。As shown in Fig. 2G, the second hard mask layer 302 is patterned and etched, which generally includes defining the shallow trench isolation formation area by using a photolithography process, and then etching the second hard mask layer 302 according to the photolithography definition to open the shallow trench isolation formation area.

如图2H所示,以图形化后的所述第二硬质掩膜层302为掩膜对底部的氧化层如所述高压栅氧化层104a或所述中压栅氧化层104b以及所述半导体衬底101进行刻蚀形成浅沟槽105a和105b。由于所述高压栅氧化层104a和所述中压栅氧化层104b之间具有不同的厚度,故浅沟槽105a和105b之间具有不同的深度。As shown in Fig. 2H, the bottom oxide layer such as the high voltage gate oxide layer 104a or the medium voltage gate oxide layer 104b and the semiconductor substrate 101 are etched to form shallow trenches 105a and 105b using the patterned second hard mask layer 302 as a mask. Since the high voltage gate oxide layer 104a and the medium voltage gate oxide layer 104b have different thicknesses, the shallow trenches 105a and 105b have different depths.

如图2I所示,在所述浅沟槽105a和105b中填充场氧分别形成所述第一浅沟槽隔离106a和所述第二浅沟槽隔离106b。As shown in FIG. 2I , field oxygen is filled in the shallow trenches 105 a and 105 b to form the first shallow trench isolation 106 a and the second shallow trench isolation 106 b , respectively.

之后,去除所述第二硬质掩膜层302。Afterwards, the second hard mask layer 302 is removed.

步骤六、在所述逻辑器件的形成区域中完成栅极导电材料层109的形成工艺之前的工艺。之后,如图2M所示,同时在所述高压CMOS的形成区域201和所述逻辑器件的形成区域中形成栅极导电材料层109。Step 6: Complete the processes before the gate conductive material layer 109 is formed in the logic device formation region. Then, as shown in FIG. 2M , the gate conductive material layer 109 is formed in the high voltage CMOS formation region 201 and the logic device formation region at the same time.

本发明实施例中,步骤六包括如下分步骤:In the embodiment of the present invention, step six includes the following sub-steps:

步骤61、如图2J所示,在所述中压CMOS的形成区域202a中形成所述中压CMOS的具有第二导电类型掺杂的第二沟道区107。Step 61 , as shown in FIG. 2J , a second channel region 107 of the medium voltage CMOS doped with a second conductivity type is formed in the medium voltage CMOS formation region 202 a .

步骤62、如图2K所示,在所述低压CMOS的形成区域202b中形成所述低压CMOS的具有第二导电类型掺杂的第三沟道区108。Step 62 , as shown in FIG. 2K , a third channel region 108 of the low voltage CMOS doped with the second conductivity type is formed in the formation region 202 b of the low voltage CMOS.

步骤63、如图2L所示,去除所述低压CMOS的形成区域202b中的所述中压栅氧化层104b。Step 63, as shown in FIG. 2L, the medium voltage gate oxide layer 104b in the low voltage CMOS formation region 202b is removed.

步骤64、如图2L所示,进行第三次热氧化工艺在所述低压CMOS的形成区域202b的所述半导体衬底101表面形成低压栅氧化层202c。Step 64, as shown in FIG. 2L, a third thermal oxidation process is performed to form a low-voltage gate oxide layer 202c on the surface of the semiconductor substrate 101 in the low-voltage CMOS formation region 202b.

步骤65、形成所述栅极导电材料层109并对所述栅极导电材料层109进行图形化刻蚀,将图形化后的所述栅极导电材料层109所覆盖区域外的所述高压栅氧化层104a、所述中压栅氧化层104b和所述低压栅氧化层202c去除。Step 65, forming the gate conductive material layer 109 and performing patterning and etching on the gate conductive material layer 109, and removing the high voltage gate oxide layer 104a, the medium voltage gate oxide layer 104b and the low voltage gate oxide layer 202c outside the area covered by the patterned gate conductive material layer 109.

较佳为,所述栅极导电材料层109采用多晶硅栅。Preferably, the gate conductive material layer 109 is made of polysilicon gate.

步骤七、如图2N所示,进行第一导电类型重掺杂的源漏注入同时在所述高压CMOS的形成区域201和所述逻辑器件的形成区域形成源漏区110。Step 7, as shown in FIG. 2N , a heavily doped source/drain implantation of the first conductivity type is performed to simultaneously form source/drain regions 110 in the high voltage CMOS formation region 201 and the logic device formation region.

本发明实施例中,所述高压CMOS包括高压NMOS和高压PMOS。In the embodiment of the present invention, the high-voltage CMOS includes a high-voltage NMOS and a high-voltage PMOS.

对于所述高压NMOS,第一导电类型为N型,第二导电类型为P型。For the high-voltage NMOS, the first conductivity type is N-type, and the second conductivity type is P-type.

对于所述高压PMOS,第一导电类型为P型,第二导电类型为N型。For the high-voltage PMOS, the first conductivity type is P-type, and the second conductivity type is N-type.

步骤一中,所述高压NMOS的所述第一沟道区102和所述高压PMOS的所述第一沟道区102分开进行。In step 1, the first channel region 102 of the high voltage NMOS and the first channel region 102 of the high voltage PMOS are processed separately.

步骤二中,所述高压NMOS的所述第一漂移区103和所述高压PMOS的所述第一漂移区103分开进行。In step 2, the first drift region 103 of the high voltage NMOS and the first drift region 103 of the high voltage PMOS are processed separately.

步骤三和步骤四中,所述高压NMOS和所述高压PMOS的形成区域的工艺同时进行。In step 3 and step 4, the processes of forming the high voltage NMOS and the high voltage PMOS regions are performed simultaneously.

所述中压CMOS包括中压NMOS和中压PMOS;The medium voltage CMOS includes a medium voltage NMOS and a medium voltage PMOS;

对于所述中压NMOS,第一导电类型为N型,第二导电类型为P型;For the medium voltage NMOS, the first conductivity type is N type, and the second conductivity type is P type;

对于所述中压PMOS,第一导电类型为P型,第二导电类型为N型。For the medium voltage PMOS, the first conductivity type is P type, and the second conductivity type is N type.

步骤61中,所述中压NMOS的所述第二沟道区107和所述中压PMOS的所述第二沟道区107分开进行。In step 61 , the second channel region 107 of the medium voltage NMOS and the second channel region 107 of the medium voltage PMOS are processed separately.

所述低压CMOS包括低压NMOS和低压PMOS;The low voltage CMOS includes a low voltage NMOS and a low voltage PMOS;

对于所述低压NMOS,第一导电类型为N型,第二导电类型为P型;For the low voltage NMOS, the first conductivity type is N type, and the second conductivity type is P type;

对于所述低压PMOS,第一导电类型为P型,第二导电类型为N型。For the low voltage PMOS, the first conductivity type is P type, and the second conductivity type is N type.

步骤62中,所述低压NMOS的所述第三沟道区108和所述低压PMOS的所述第三沟道区108分开进行。In step 62 , the third channel region 108 of the low voltage NMOS and the third channel region 108 of the low voltage PMOS are processed separately.

步骤64中,所述低压NMOS和所述低压PMOS的形成区域的工艺同时进行。In step 64 , the processes of forming the low voltage NMOS and the low voltage PMOS regions are performed simultaneously.

本发明实施例中,所述高压CMOS应用于屏幕显示驱动芯片中。In an embodiment of the present invention, the high-voltage CMOS is applied to a screen display driver chip.

本发明实施例对逻辑器件和高压CMOS的集成工艺中的工艺顺序做了特别的设置,将高压CMOS中为满足高压CMOS的耐压性能而必须采用的热过程即第一热过程和第二热过程都放置在浅沟槽隔离的形成工艺之前,这样就能避免在第一热过程和第二热过程中会出现有源区和浅沟槽隔离的不同材料的热膨胀系数不同而出现的应力,从而能消除有源区受到应力作用而产生缺陷和位错。The embodiment of the present invention makes a special arrangement for the process sequence in the integration process of the logic device and the high-voltage CMOS, and places the thermal processes that must be used in the high-voltage CMOS to meet the voltage resistance performance of the high-voltage CMOS, namely the first thermal process and the second thermal process, before the shallow trench isolation formation process. In this way, stress caused by different thermal expansion coefficients of different materials in the active area and the shallow trench isolation in the first thermal process and the second thermal process can be avoided, thereby eliminating defects and dislocations caused by stress in the active area.

同时,本发明实施例高压CMOS所需要的热过程如第一热过程和第二热过程由于不会受到对有源区产生不利影响的限制,故第一热过程和第二热过程都能充分进行,从而能使得第一漂移区103的掺杂均匀性得到充分提升,高压栅氧化层104a的厚度也能增加到耐压要求值,最后能提升高压CMOS的耐压性能。At the same time, the thermal processes required by the high-voltage CMOS in the embodiment of the present invention, such as the first thermal process and the second thermal process, are not restricted by the adverse effects on the active area, so the first thermal process and the second thermal process can be fully carried out, so that the doping uniformity of the first drift region 103 can be fully improved, and the thickness of the high-voltage gate oxide layer 104a can also be increased to the required withstand voltage value, and finally the withstand voltage performance of the high-voltage CMOS can be improved.

另外,本发明实施例的第一次热氧化工艺由于放置在浅沟槽隔离形成之前,能防止出现浅沟槽隔离边缘对高压栅氧化层104a的厚度降低的情形,最后能使高压栅氧化层104a在各区域的厚度均匀,从而能提升高压栅氧化层104a的质量。In addition, since the first thermal oxidation process in the embodiment of the present invention is placed before the shallow trench isolation is formed, it can prevent the shallow trench isolation edge from reducing the thickness of the high-voltage gate oxide layer 104a. Finally, the thickness of the high-voltage gate oxide layer 104a in each area can be made uniform, thereby improving the quality of the high-voltage gate oxide layer 104a.

另外,本发明实施例的高压栅氧化层104a形成在浅沟槽隔离之前,这样在浅沟槽隔离形成过程中,采用相同的刻蚀工艺形成浅沟槽时,形成有高压栅氧化层104a的区域和未形成高压栅氧化层104a的区域会得到不同的浅沟槽深度,且高压栅氧化层104a的区域的浅沟槽的深度会更浅,所以高压CMOS的浅沟槽隔离即第一浅沟槽隔离106a的深度会更浅,这和高压CMOS对设置在漂移区中的第一浅沟槽隔离106a的深度要求相符合,因为这有利于降低导通电阻,故本发明实施例能节省制造不同深度的浅沟槽隔离的工艺成本。In addition, the high-voltage gate oxide layer 104a of the embodiment of the present invention is formed before the shallow trench isolation. In this way, during the shallow trench isolation formation process, when the shallow trench is formed using the same etching process, the area where the high-voltage gate oxide layer 104a is formed and the area where the high-voltage gate oxide layer 104a is not formed will obtain different shallow trench depths, and the depth of the shallow trench in the area where the high-voltage gate oxide layer 104a is formed will be shallower, so the depth of the shallow trench isolation of the high-voltage CMOS, that is, the first shallow trench isolation 106a, will be shallower, which is consistent with the depth requirement of the high-voltage CMOS for the first shallow trench isolation 106a set in the drift region. Because this is conducive to reducing the on-resistance, the embodiment of the present invention can save the process cost of manufacturing shallow trench isolations of different depths.

以上通过具体实施例对本发明进行了详细的说明,但这些并非构成对本发明的限制。在不脱离本发明原理的情况下,本领域的技术人员还可做出许多变形和改进,这些也应视为本发明的保护范围。The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims (15)

1. A process integration method for integrating high-voltage CMOS in a logic process is characterized in that the working voltage of a logic device is smaller than that of the high-voltage CMOS, and comprises the following steps:
step one, forming a second conduction type doped first channel region in a semiconductor substrate of a selected area of a formation area of the high-voltage CMOS;
Step two, forming a first drift region doped with a first conductivity type in the semiconductor substrate of a selected region of the formation region of the high-voltage CMOS;
Step three, performing a first furnace tube hot-push trap, wherein the furnace tube hot-push trap has a first thermal process, the more the first thermal process is, the better the doping uniformity of the first drift region is, and the first thermal process is increased to enable the doping uniformity of the first drift region to be improved to meet the pressure-resistant requirement of the high-voltage CMOS;
Forming a high-voltage gate oxide layer on the surface of the semiconductor substrate in the formation area of the high-voltage CMOS by adopting a first thermal oxidation process, wherein the first thermal oxidation process has a second thermal process, the more the second thermal process is, the thicker the thickness of the high-voltage gate oxide layer is, and the second thermal process is increased to enable the high-voltage gate oxide layer to meet the pressure-resistant requirement of the high-voltage CMOS;
Forming shallow trench isolation, wherein the shallow trench isolation comprises a first shallow trench isolation positioned in a forming area of the high-voltage CMOS and a second shallow trench isolation positioned in a forming area of the logic device, and the depth of the first shallow trench isolation is smaller than that of the second shallow trench isolation by utilizing the characteristic that the high-voltage gate oxide layer is formed in the forming area of the high-voltage CMOS before the shallow trench isolation is formed;
The semiconductor substrate of the area surrounded by the shallow trench isolation is used as an active area, and the characteristics that the first thermal process and the second thermal process are positioned before the shallow trench isolation forming process are utilized to reduce the stress born by the active area and eliminate the defects of the active area caused by the stress;
The first thermal oxidation process is placed before the shallow trench isolation forming process, so that the thickness of the high-voltage gate oxide layer is ensured not to be affected by the edges of the shallow trench isolation, and the uniformity of the high-voltage gate oxide layer is improved;
step six, completing the process before the forming process of the gate conductive material layer in the forming area of the logic device, and then forming the gate conductive material layer in the forming area of the high-voltage CMOS and the forming area of the logic device at the same time;
And step seven, carrying out the source-drain injection of the first conductive type heavy doping and simultaneously forming a source-drain region in the forming region of the high-voltage CMOS and the forming region of the logic device.
2. The process integration method for integrating high voltage CMOS in a logic process according to claim 1, wherein: the logic device comprises a medium voltage CMOS and a low voltage CMOS, wherein the working voltage of the medium voltage CMOS is smaller than that of the high voltage CMOS, and the working voltage of the medium voltage CMOS is larger than that of the low voltage CMOS.
3. The process integration method for integrating high voltage CMOS in a logic process according to claim 2, wherein: the medium-voltage gate oxide layer of the medium-voltage CMOS is formed by adopting a second thermal oxidation process, and the second thermal oxidation process is placed after the first thermal oxidation process in the fourth step and before the shallow trench isolation forming process in the fifth step; the thickness of the medium voltage gate oxide layer is thinner than that of the high voltage gate oxide layer;
The second thermal oxidation process has a third thermal process, and the characteristics that the third thermal process is positioned before the shallow trench isolation forming process are utilized to reduce the stress born by the active region and eliminate the defect of the active region caused by the stress;
And simultaneously, the second thermal oxidation process is used for being placed before the shallow trench isolation forming process to ensure that the thickness of the medium voltage gate oxide layer is not influenced by the edges of the shallow trench isolation, so that the uniformity of the medium voltage gate oxide layer is improved.
4. A process integration method for integrating high voltage CMOS in a logic process as claimed in claim 3, wherein: step six comprises the following sub-steps:
step 61, forming a second channel region of the medium voltage CMOS with second conductivity type doping in a forming region of the medium voltage CMOS;
step 62, forming a third channel region of the low-voltage CMOS with second conductivity type doping in a forming region of the low-voltage CMOS;
Step 63, removing the medium voltage gate oxide layer in the forming area of the low voltage CMOS;
step 64, performing a third thermal oxidation process to form a low-voltage gate oxide layer on the surface of the semiconductor substrate in the formation region of the low-voltage CMOS;
and step 65, forming the gate conductive material layer, performing patterned etching on the gate conductive material layer, and removing the high-voltage gate oxide layer, the medium-voltage gate oxide layer and the low-voltage gate oxide layer outside the coverage area of the patterned gate conductive material layer.
5. A process integration method for integrating high voltage CMOS in a logic process as claimed in claim 3, wherein: the gate conductive material layer adopts a polysilicon gate.
6. The process integration method for integrating high voltage CMOS in a logic process according to claim 1, wherein: the semiconductor substrate includes a silicon substrate.
7. A process integration method for integrating high voltage CMOS in a logic process as claimed in claim 1 or 4, wherein: the high-voltage CMOS comprises a high-voltage NMOS and a high-voltage PMOS;
for the high-voltage NMOS, the first conductivity type is N type, and the second conductivity type is P type;
For the high voltage PMOS, the first conductivity type is P-type and the second conductivity type is N-type.
8. The process integration method for integrating high voltage CMOS in a logic process as recited in claim 7, wherein: in the first step, the first channel region of the high-voltage NMOS and the first channel region of the high-voltage PMOS are performed;
In the second step, the first drift region of the high-voltage NMOS and the first drift region of the high-voltage PMOS are performed separately.
9. The process integration method for integrating high voltage CMOS in a logic process according to claim 8, wherein:
in the third and fourth steps, the processes of forming the regions of the high-voltage NMOS and the high-voltage PMOS are performed simultaneously.
10. The process integration method for integrating high voltage CMOS in a logic process according to claim 4, wherein: the medium voltage CMOS comprises a medium voltage NMOS and a medium voltage PMOS;
For the medium-voltage NMOS, the first conductivity type is N type, and the second conductivity type is P type;
for the medium voltage PMOS, the first conductivity type is P-type and the second conductivity type is N-type.
11. The process integration method for integrating high voltage CMOS in a logic process of claim 10, wherein: in step 61, the second channel region of the medium voltage NMOS and the second channel region of the medium voltage PMOS are performed separately.
12. The process integration method for integrating high voltage CMOS in a logic process according to claim 4, wherein: the low-voltage CMOS comprises a low-voltage NMOS and a low-voltage PMOS;
for the low-voltage NMOS, the first conductivity type is N type, and the second conductivity type is P type;
for the low voltage PMOS, the first conductivity type is P-type and the second conductivity type is N-type.
13. The process integration method for integrating high voltage CMOS in a logic process of claim 12, wherein: in step 62, the third channel region of the low voltage NMOS and the third channel region of the low voltage PMOS are performed separately.
14. The process integration method for integrating high voltage CMOS in a logic process of claim 12, wherein: in step 64, the process of forming the low-voltage NMOS and the low-voltage PMOS is performed simultaneously.
15. The process integration method for integrating high voltage CMOS in a logic process according to claim 1, wherein: the high-voltage CMOS is adopted in the screen display driving chip.
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