CN113658865B - Method for forming semiconductor structure - Google Patents

Abstract

A method for forming a semiconductor structure, comprising: forming a plurality of first openings in the dielectric layer, the bottom of each of the first openings exposing a top surface of a first source-drain doped region; forming a plurality of second openings in the dielectric layer, the bottom of each of the second openings exposing a partial surface of a top of a first gate structure; forming a plurality of third openings in the dielectric layer, the bottom of the third openings being higher than the top surface of the first gate layer, and the third openings being connected to the first opening and the second openings, respectively. The method can reduce the mutual influence between different processes, so that the performance of the formed semiconductor structure is better.

Description

Method for forming semiconductor structure

Technical Field

The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure.

Background Art

With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving towards higher component density and higher integration. Transistors, as the most basic semiconductor devices, are currently being widely used. Traditional planar devices have weakened their ability to control channel current, resulting in short channel effects and leakage current, which ultimately affects the electrical performance of semiconductor devices.

In order to overcome the short channel effect of transistors and suppress leakage current, the prior art proposes a fin field effect transistor (Fin FET). The fin field effect transistor is a common multi-gate device. The structure of the fin field effect transistor includes: a fin and an isolation layer located on the surface of a semiconductor substrate, the isolation layer covers a portion of the side wall of the fin, and the surface of the isolation layer is lower than the top of the fin; a gate structure located on the surface of the isolation layer, and the top and side wall surfaces of the fin; and a source and drain doped region in the fin located on both sides of the gate structure.

However, when the source/drain doped regions and the gate structure are electrically connected to the peripheral circuit via a common plug, the performance of the conventionally formed semiconductor structure is relatively poor.

Summary of the invention

The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a dense area; forming a plurality of first gate structures located on the substrate, a plurality of first source-drain doped regions located in the substrate, and a dielectric layer located on the substrate, the first gate structure is located on the dense area, the first gate structure includes a first gate layer, and the substrate on both sides of each first gate structure has a first source-drain doped region, the dielectric layer is located on the surface of the first gate structure and the surface of the first source-drain doped region; forming a plurality of first openings in the dielectric layer, the bottom of each first opening exposes a top surface of the first source-drain doped region; forming a plurality of second openings in the dielectric layer, the bottom of each second opening exposes a portion of the top surface of the first gate structure; forming a plurality of third openings in the dielectric layer, the bottom of the third opening is higher than the top surface of the first gate layer, each of the third openings is located between adjacent first openings and second openings, and the third openings are respectively connected to the first openings and the second openings.

Optionally, after forming the first opening, the second opening is formed.

Optionally, the substrate also includes a sparse area; the substrate also has a plurality of second gate structures and a plurality of second source-drain doped regions located in the substrate, the second gate structure is located on the dense area, the second gate structure includes a second gate layer, and the substrate on both sides of each second gate structure has a second source-drain doped region respectively; the dielectric layer is located on the surface of the second gate structure and the surface of the second source-drain doped region.

Optionally, it also includes: forming a plurality of fourth openings in the dielectric layer, the bottom of each of the fourth openings exposing a top surface of a second source-drain doped region; forming a plurality of fifth openings in the dielectric layer, the bottom of each of the fifth openings exposing a portion of the top surface of a second gate structure, and the fourth openings and the fifth openings are separated from each other; forming a plurality of sixth openings in the dielectric layer, the bottom of the sixth openings being higher than the top surface of the second gate layer, each of the sixth openings being located between adjacent fourth openings and fifth openings, and the sixth openings are respectively connected to the fourth opening and the fifth opening.

Optionally, the first opening and the fourth opening are formed simultaneously; the second opening and the fifth opening are formed simultaneously; and the third opening and the sixth opening are formed simultaneously.

Optionally, the method for forming the first opening and the fourth opening includes: forming a first patterned layer on the surface of the dielectric layer, the first patterned layer exposing the surface of the dielectric layer on the first source and drain doping regions and the second source and drain doping regions; using the first patterned layer as a mask, etching the dielectric layer until the top surfaces of the first source and drain doping regions and the second source and drain doping regions are exposed, forming the first opening in the dense area, and forming the fourth opening in the sparse area.

Optionally, the method for forming the second opening and the fifth opening includes: forming a second patterned layer on the dielectric layer, the second patterned layer exposing the surface of the dielectric layer on the first gate structure and the second gate structure; using the second patterned layer as a mask, etching the dielectric layer until the top surfaces of the first gate structure and the second gate structure are exposed, forming the second opening in the dense area, and forming the fifth opening in the sparse area.

Optionally, it also includes: after forming the first opening and before forming the second opening, forming a first planarization layer in the first opening and on the surface of the dielectric layer; the second patterned layer is located on the surface of the first planarization layer; after forming the second opening, removing the first planarization layer.

Optionally, a material of the first planarization layer is different from a material of the dielectric layer.

Optionally, the material of the first planarization layer includes: an organic material containing carbon and oxygen.

Optionally, the method for forming the third opening and the sixth opening includes: forming a third patterned layer on the dielectric layer, the third patterned layer exposing the surface of the dielectric layer between the first opening and the second opening, and the surface of the dielectric layer between the fourth opening and the fifth opening; using the third patterned layer as a mask, etching the dielectric layer to form the third opening in a dense area and forming the sixth opening in a sparse area.

Optionally, it also includes: after forming the second opening and before forming the third opening, forming a second planarization layer on the first opening, the second opening, and the surface of the dielectric layer; the third patterned layer is located on the surface of the second planarization layer; after forming the third opening, removing the second planarization layer.

Optionally, a material of the second planarization layer is different from a material of the dielectric layer.

Optionally, the material of the second planarization layer includes: an organic material containing carbon and oxygen.

Optionally, the aspect ratio of the third opening ranges from 2:9 to 8:3.

Optionally, a distance between adjacent first gate structures is smaller than a distance between adjacent second gate structures.

Optionally, the base includes a substrate and a plurality of fins located on the surface of the substrate, the first gate structure spans across the plurality of fins, and the first gate structure covers a portion of the top surface and side wall surface of the fins; the first source and drain doping regions are located in the fins on both sides of the first gate structure.

Optionally, the formation process of the first patterned layer includes: extreme ultraviolet lithography process; the formation process of the second patterned layer includes: extreme ultraviolet lithography process; the formation process of the third patterned layer includes: extreme ultraviolet lithography process.

Optionally, the method further includes: filling the first opening, the second opening and the third opening with conductive material to form a conductive structure.

Optionally, the dielectric layer includes: a first dielectric layer, an etch stop layer located on a surface of the first dielectric layer, and a second dielectric layer located on a surface of the etch stop layer.

Optionally, the first gate structure further includes: a first gate dielectric layer located at the bottom of the first gate layer, and a first barrier layer located on the top surface of the first gate dielectric layer and the top surface of the first gate layer.

Optionally, the method for forming the first gate structure, the first source-drain doped region, and the dielectric layer includes: forming a first dummy gate structure on the substrate; forming a first source-drain doped region in the substrate on both sides of the first dummy gate structure; forming a first dielectric layer on the substrate, the first dielectric layer being located on the surface of the first dummy gate structure and the surface of the first source-drain doped region; removing the first dummy gate structure to form a first dummy gate opening in the first dielectric layer; forming a first gate dielectric layer, a first gate layer located on the surface of the first gate dielectric layer, and a first barrier layer located on the top surface of the first gate dielectric layer and the top surface of the first gate layer in the first dummy gate opening; forming an etch stop layer on the surface of the first barrier layer and the surface of the first dielectric layer; and forming the second dielectric layer on the surface of the etch stop layer.

Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

In the method for forming a semiconductor structure provided by the technical solution of the present invention, a first opening exposing the top surface of the first source-drain doped region, a second opening exposing the top surface of the first gate structure, and a third opening located between the adjacent first opening and the second opening are formed in different processes respectively. Since the third opening is connected to the first opening and the second opening respectively, the third opening can connect the first opening and the second opening, so that the conductive structure subsequently formed in the first opening, the second opening and the third opening can realize the simultaneous electrical connection of the first gate structure and the first source-drain doped region, thereby meeting the process requirements. At the same time, the first opening, the second opening and the third opening are completed in three different etching processes, which can reduce the impact caused by different processes, and the bottom of the third opening is higher than the top surface of the first gate layer, which can avoid over-etching the first source-drain doped region located at the bottom of the first opening during the formation of the third opening, thereby reducing the leakage current generated between the first gate structure and the substrate, so that the performance of the formed semiconductor structure is better.

Furthermore, the substrate also includes a sparse area, the sparse area has a second gate structure, and the substrate on both sides of the second gate structure has a second source-drain doped area. Since the first opening and the fourth opening are formed at the same time, the second opening and the fifth opening are formed at the same time, the third opening and the sixth opening are formed at the same time, and the first opening and the fourth opening are formed in the dense area and the sparse area, the second opening and the fifth opening, and the third opening and the sixth opening are completed in different processes, which is conducive to reducing the impact on different processes, so that in the process of forming the fifth opening in the dense area and the sixth opening in the sparse area, the first source-drain doped area at the bottom of the first opening and the second source-drain doped area at the bottom of the fourth opening will not be over-etched, thereby reducing the leakage current between the first gate structure and the substrate, and between the second gate structure and the substrate, so that the performance of the formed semiconductor structure is better.

BRIEF DESCRIPTION OF THE DRAWINGS

1 to 4 are schematic structural diagrams of various steps of a method for forming a semiconductor structure;

5 to 15 are schematic structural diagrams of various steps of a method for forming a semiconductor structure in an embodiment of the present invention.

DETAILED DESCRIPTION

First, the reasons why the performance of the existing semiconductor structure is poor are described in detail with reference to the accompanying drawings. FIG. 1 to FIG. 4 are schematic structural diagrams of various steps of a method for forming an existing semiconductor structure.

Please refer to Figure 1, a substrate 100 is provided, and the substrate 100 includes a dense area A and a sparse area B. The dense area A has a plurality of first gate structures 111, and the substrate 100 on both sides of the first gate structure 111 respectively has a first source-drain doping region 121, and the sparse area B has a plurality of second gate structures 112, and the substrate 100 on both sides of the second gate structure 112 respectively has a second source-drain doping region 122.

Referring to FIG. 2 , a dielectric layer 130 is formed on the substrate 100 , and the dielectric layer 130 is located on the surfaces of the first gate structure 111 and the first source-drain doped region 121 , the second gate structure 112 , and the second source-drain doped region 122 .

3 , a plurality of first openings 141 and second openings 142 are formed in the dielectric layer 130 , the bottom of each first opening 141 exposes a top surface of a first source/drain doped region 121 , and the bottom of each second opening 142 exposes a top surface of a second source/drain doped region 122 .

Please refer to Figure 4. After the first opening 141 and the second opening 142 are formed, a third opening 151 exposing the top surface of the first gate structure 111 and a fourth opening 152 exposing the top surface of the second gate structure 112 are formed in the dielectric layer 130, and the third opening 151 overlaps with a portion of the first opening 141, and the fourth opening 152 overlaps with a portion of the second opening 142.

In the above method, by making the third opening 151 overlap with a portion of the first opening 141, and the fourth opening 152 overlap with a portion of the second opening 142, the plugs subsequently formed in the first opening 141 and the third opening 151 can be electrically connected to the first source-drain doping region 121 and the first gate structure 111 at the same time, and the plugs formed in the second opening 142 and the fourth opening 152 can be electrically connected to the second source-drain doping region 122 and the second gate structure 112 at the same time, thereby meeting specific process requirements.

However, the existing method for forming the third opening 151 and the fourth opening 152 is: forming a planarization layer (not shown in the figure) on the first opening 141, the second opening 142, and the surface 130 of the dielectric layer; forming a patterned layer (not shown in the figure) on the surface of the planarization layer, the patterned layer exposing the first opening 141 and the first gate structure 111 in the dense area A, and the planarization layer surface on the dielectric layer 130 between the adjacent first openings 141 and the first gate structure 111, and the planarization layer surface on the second opening 142 and the second gate structure 112 in the sparse area B, and the planarization layer surface on the dielectric layer 130 between the adjacent second openings 142 and the second gate structure 112; using the patterned layer as a mask, etching the dielectric layer 130 and the planarization layer until the top surface of the first gate structure 111 and the top surface of the second gate structure 112 are exposed, forming the third opening 151 in the dense area A, and forming the fourth opening 152 in the sparse area B.

Since the device density of the dense area A is greater than that of the sparse area B, the thickness of the planarization layer filled in the first opening 141 and the second opening 142 and higher than the surface of the dielectric layer 130 is different in the dense area A and the sparse area B. Specifically, the thickness of the planarization layer on the dense area A is less than the thickness of the planarization layer on the sparse area B. As a result, in the process of forming the third opening 151 and the fourth opening 152 by etching the dielectric layer 130 and the planarization layer, in order to ensure that the fourth opening 152 located in the sparse area B can expose the top surface of the second gate structure 112, it is easy to cause over-etching of the dense area A where the thickness of the planarization layer is thinner, and then it is easy to cause etching damage to the first source-drain doped region 121 at the bottom of the first opening 141, resulting in leakage current between the first gate structure 111 and the substrate 100, affecting the power consumption of the device, which is not conducive to the performance of the semiconductor structure.

In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, wherein a plurality of first openings are formed in the dielectric layer, and the bottom of each of the first openings exposes a top surface of a first source-drain doped region; a plurality of second openings are formed in the dielectric layer, and the bottom of each of the second openings exposes a partial surface of the top of a first gate structure; a plurality of third openings are formed in the dielectric layer, and the bottom of the third openings is higher than the top surface of the first gate layer, and the third openings are respectively connected to the first opening and the second opening. The first opening, the second opening, and the third opening are completed in three different etching processes, which can reduce the mutual influence between different processes, so that the performance of the formed semiconductor structure is better.

In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

5 to 15 are schematic structural diagrams of various steps of a method for forming a semiconductor structure in an embodiment of the present invention.

Referring to FIG. 5 , a substrate 200 is provided. The substrate 200 includes a dense area A.

In this embodiment, the substrate 200 further includes: a sparse area B.

The base 200 includes a substrate and a plurality of fins located on a surface of the substrate.

In other embodiments, the substrate has no fins thereon.

In this embodiment, the method for forming the base 200 includes: providing an initial substrate (not shown); the initial substrate has a mask layer, and the mask layer exposes a portion of the surface of the initial substrate; using the mask layer as a mask, etching the initial substrate to form a substrate and a fin located on the surface of the substrate.

In this embodiment, the material of the initial substrate is silicon. Accordingly, the material of the substrate and the fin is silicon.

In other embodiments, the material of the initial substrate includes: germanium, silicon germanium, silicon on insulator or germanium on insulator. Correspondingly, the material of the substrate includes: germanium, silicon germanium, silicon on insulator or germanium on insulator. The material of the fin includes: germanium, silicon germanium, silicon on insulator or germanium on insulator.

Please refer to Figure 6, a plurality of first gate structures 211 located on the substrate 200, a plurality of first source-drain doped regions 221 located in the substrate 200, and a dielectric layer 230 located on the substrate 200 are formed, the first gate structure 211 is located on the dense area A, the first gate structure 211 includes a first gate layer 2111, and the substrate 200 on both sides of each first gate structure 211 has a first source-drain doped region 221, and the dielectric layer 230 is located on the surface of the first gate structure 211 and the surface of the first source-drain doped region 221.

In this embodiment, the semiconductor structure also includes: a plurality of second gate structures 212 located on the substrate 200, and a plurality of second source-drain doped regions 222 located in the substrate 200, wherein the second gate structure 212 is located on the sparse area B, the second gate structure 212 includes a second gate layer 2121, and each of the second gate structures 212 has a second source-drain doped region 222 in the substrate 200 on both sides; the dielectric layer 230 is located on the surface of the second gate structure 212 and the surface of the second source-drain doped region 222.

In this embodiment, the base 200 includes a substrate and a plurality of fins located on the surface of the substrate, the first gate structure 211 spans across the plurality of fins, and the first gate structure 211 covers a portion of the top surface and side wall surface of the fins; the first source and drain doping regions 221 are located in the fins on both sides of the first gate structure 211.

The distance between adjacent first gate structures 211 is smaller than the distance between adjacent second gate structures 212 , so that the device density formed on the dense area A is greater than the device density formed on the sparse area B.

The dielectric layer 230 includes: a first dielectric layer (not shown in the figure), an etch stop layer (not shown in the figure) located on the surface of the first dielectric layer, and a second dielectric layer (not shown in the figure) located on the surface of the etch stop layer.

Specifically, in this embodiment, the first gate structure 211 further includes: a first gate dielectric layer 2112 located at the bottom of the first gate layer 2111 , and a first blocking layer 2113 located on the top surfaces of the first gate dielectric layer 2112 and the first gate layer 2111 .

The material of the first gate dielectric layer 2112 includes: a high-K dielectric material, and the high-K dielectric material includes: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide. In this embodiment, the material of the first gate dielectric layer 2112 is hafnium oxide.

The material of the first gate layer 2111 includes metal, and the metal includes one or more combinations of copper, tungsten, aluminum, titanium, nickel, titanium nitride and tantalum nitride. In this embodiment, the material of the first gate layer 2111 is tungsten.

The material of the first barrier layer 2113 includes silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide. In this embodiment, the material of the first barrier layer 2113 is silicon nitride oxide.

The first barrier layer 2113 is used to protect the surface of the first gate layer 2111, which is beneficial for the first gate layer 2111 to maintain its morphology and reduce the generation of defects.

The method for forming the first gate structure 211, the first source-drain doped region 221, and the dielectric layer 230 includes: forming a first dummy gate structure (not shown in the figure) on the substrate 200; forming a first source-drain doped region 221 in the substrate 200 on both sides of the first dummy gate structure; forming a first dielectric layer on the substrate 200, the first dielectric layer being located on the surface of the first dummy gate structure and the surface of the first source-drain doped region 221; removing the first dummy gate structure and forming a first dummy gate opening in the first dielectric layer (not shown in the figure); forming a first gate dielectric layer 2112, a first gate layer 2111 located on the surface of the first gate dielectric layer 2112, and a first barrier layer 2113 located on the top surface of the first gate dielectric layer 2112 and the top surface of the first gate layer 2111 in the first dummy gate opening; forming an etch stop layer on the surface of the first barrier layer 2113 and the surface of the first dielectric layer; and forming the second dielectric layer on the surface of the etch stop layer.

The material of the dielectric layer 230 includes silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

In this embodiment, the material of the dielectric layer 230 is an oxide layer.

The etching stop layer serves as a stop layer for subsequently forming the third opening.

Specifically, in this embodiment, the second gate structure 212 further includes: a second gate dielectric layer 2122 located at the bottom of the second gate layer 2121 , and a second blocking layer 2123 located at the top surface of the second gate dielectric layer 2122 and the top surface of the second gate layer 2121 .

The material of the second gate dielectric layer 2122 is the same as that of the first gate dielectric layer 2112 , and will not be described in detail herein.

The material of the second gate layer 2121 is the same as that of the first gate layer 2111 , and will not be described in detail herein.

The material of the second barrier layer 2123 is the same as that of the first barrier layer 2113 and will not be described in detail herein.

Please refer to Figures 7 and 8, Figure 8 is a cross-sectional schematic diagram of Figure 7 along the X-X1 and Y-Y1 tangent directions, and a plurality of first openings 241 are formed in the dielectric layer 230, and the bottom of each of the first openings 241 exposes a top surface of a first source-drain doped region 221.

In this embodiment, the method for forming the semiconductor structure further includes: forming a plurality of fourth openings 244 in the dielectric layer 230 , wherein the bottom of each of the fourth openings 244 exposes a top surface of a second source/drain doped region 222 .

The first opening 241 and the fourth opening 244 are formed simultaneously.

The method for forming the first opening 241 and the fourth opening 244 includes: forming a first patterned layer (not shown in the figure) on the surface of the dielectric layer 230, the first patterned layer exposing the surface of the dielectric layer 230 on the first source and drain doping regions 221 and the second source and drain doping regions 222; using the first patterned layer as a mask, etching the dielectric layer 230 until the top surfaces of the first source and drain doping regions 221 and the second source and drain doping regions 222 are exposed, forming the first opening 241 in the dense area A, and forming the fourth opening 244 in the sparse area B.

The process of etching the dielectric layer 230 includes: an anisotropic dry etching process.

The process for forming the first patterned layer includes: extreme ultraviolet lithography process.

The material of the first graphic layer includes: photoresist.

In this embodiment, after forming the first opening 241 and the fourth opening 244 , the process further includes: removing the first patterned layer.

In this embodiment, the process of removing the first patterned layer is an ashing process.

Please refer to FIG. 9 and FIG. 10 . FIG. 9 is viewed in the same direction as FIG. 7 , and FIG. 10 is viewed in the same direction as FIG. 8 . A first planarization layer 250 is formed in the first opening 241 and on the surface of the dielectric layer 230 .

The material of the first planarization layer 250 is different from the material of the dielectric layer 230 .

The material of the first planarization layer 250 includes: an organic material containing carbon and oxygen.

In this embodiment, the material of the first planarization layer 250 is a bottom anti-reflection material.

The process of forming the first planarization layer 250 includes a spin coating process.

Please refer to FIG. 11 , which is viewed in the same direction as FIG. 9 . A plurality of second openings 242 are formed in the dielectric layer 230 . The bottom of each of the second openings 242 exposes a portion of the top surface of a first gate structure 211 .

In this embodiment, the method for forming the semiconductor structure further includes: forming a plurality of fifth openings 245 in the dielectric layer 230 , wherein the bottom of each fifth opening 245 exposes a portion of the top surface of a second gate structure 212 , and the fourth opening 244 and the fifth opening 245 are separated from each other.

The second opening 242 and the fifth opening 245 are formed simultaneously.

The method for forming the second opening 242 and the fifth opening 245 includes: forming a second patterned layer 252 on the dielectric layer 230, wherein the second patterned layer 252 exposes the surface of the dielectric layer 230 on the first gate structure 211 and the second gate structure 212; using the second patterned layer 252 as a mask, etching the dielectric layer 230 until the top surfaces of the first gate structure 211 and the second gate structure 212 are exposed, thereby forming the second opening 242 in the dense area A and forming the fifth opening 245 in the sparse area B.

Specifically, in this embodiment, the dielectric layer 230 is etched until the top surfaces of the first gate layer 2111 and the second gate layer 2121 are exposed.

The formation process of the second patterned layer 252 includes: extreme ultraviolet lithography process.

Specifically, the second patterned layer 252 is located on the surface of the first planarization layer 250 .

After forming the second opening 242 , the first planarization layer 250 is removed.

In this embodiment, after the second opening 242 and the fifth opening 245 are formed, the second patterned layer 252 is removed; and after the second patterned layer 252 is removed, the first planarization layer 250 is removed.

In this embodiment, the process of removing the second patterned layer 252 and the first planarization layer 250 is an ashing process.

Please refer to FIG. 12 , which is viewed from the same direction as FIG. 11 . A second planarization layer 260 is formed on the first opening 241 , the second opening 242 , and the surface of the dielectric layer 230 .

The material of the second planarization layer 260 is different from the material of the dielectric layer 230 .

The material of the second planarization layer 260 includes: an organic material containing carbon and oxygen.

In this embodiment, the material of the second planarization layer 260 is a bottom anti-reflection material.

The process of forming the second planarization layer 260 includes a spin coating process.

Please refer to Figures 13 and 14. The viewing directions of Figures 13 and 9 are the same, and the viewing directions of Figures 14 and 10 are the same. A plurality of third openings 243 are formed in the dielectric layer 230. The bottoms of the third openings 243 are higher than the top surface of the first gate layer 2112. The third openings 243 are respectively connected to the first openings 241 and the second openings 242.

The aspect ratio of the third opening 243 is in a range of 2:9 to 8:3.

The significance of selecting the range is that: if the aspect ratio of the third opening 243 is greater than 8:3, the third opening 243 is too deep, and it is difficult to etch the third opening 243, thereby increasing the difficulty of the process; if the aspect ratio of the third opening 243 is less than 2:9, the third opening 243 is shallow, and the overlapping part of the third opening 243 and the first opening 241 and the second opening 242 is small, and it is easy for the third opening 243 to not be connected to the first opening 241, or the third opening 243 to not be connected to the second opening 242, so that the conductive structure formed subsequently cannot be electrically connected to the first source and drain doping region 221 and the first gate structure 211 at the same time, and problems occur in the formed semiconductor structure.

In this embodiment, the method for forming the semiconductor structure also includes: forming a plurality of sixth openings 246 in the dielectric layer 230 , the bottom of the sixth openings 246 being higher than the top surface of the second gate layer 2121 , and the sixth openings 246 being respectively connected to the fourth opening 244 and the fifth opening 245 .

The third opening 243 and the sixth opening 246 are formed simultaneously.

The method for forming the third opening 243 and the sixth opening 246 includes: forming a third patterned layer 263 on the dielectric layer 230, wherein the third patterned layer 263 exposes the surface of the dielectric layer 230 between the first opening 241 and the second opening 242, and the surface of the dielectric layer 230 between the fourth opening 244 and the fifth opening 245; using the third patterned layer 263 as a mask, etching the dielectric layer 230 to form the third opening 243 in the dense area A and the sixth opening 246 in the sparse area B.

Specifically, in this embodiment, the dielectric layer 230 is etched until the surface of the etching stop layer is exposed, the third opening 243 is formed in the dense area A, and the sixth opening 246 is formed in the sparse area B.

Specifically, the third patterned layer 263 is located on the surface of the second planarization layer 260 .

The formation process of the third patterned layer 263 includes: extreme ultraviolet lithography process.

The material of the third patterned layer 263 includes: photoresist.

After forming the third opening 243 , the second planarization layer 260 is removed.

In this embodiment, after the third opening 243 and the sixth opening 246 are formed, the third patterned layer 263 is removed; after the third patterned layer 263 is removed, the second planarization layer 260 is removed.

In this embodiment, the process of removing the third patterned layer 263 and the second planarization layer 260 is an ashing process.

The first opening 241 exposing the top surface of the first source-drain doped region 221, the second opening 242 exposing the top surface of the first gate layer 2111, and the third opening 243 located between the adjacent first opening 241 and the second opening 242 are formed in different processes. Since the third opening 243 is connected to the first opening 241 and the second opening 242 respectively, the third opening 243 can connect the first opening 241 and the second opening 242, so that the conductive structures subsequently formed in the first opening 241, the second opening 242 and the third opening 243 can realize the simultaneous electrical connection between the first gate structure 211 and the first source-drain doped region 221, thereby meeting the process requirements. At the same time, the first opening 241, the second opening 242 and the third opening 243 are completed in three different etching processes, which can reduce the impact between different processes, and the bottom of the third opening 243 is higher than the top surface of the first gate layer 2111, which can avoid over-etching the first source-drain doped region 221 located at the bottom of the first opening 241 during the formation of the third opening 243, thereby reducing the leakage current generated between the first gate structure 211 and the substrate 200, so that the performance of the formed semiconductor structure is better.

The substrate 200 further includes a sparse region B. A second gate structure 212 is formed on the sparse region B. Second source and drain doping regions 222 are respectively formed in the substrate 200 on both sides of the second gate structure 212 . Since the first opening 241 and the fourth opening 244 are formed at the same time, the second opening 242 and the fifth opening 245 are formed at the same time, the third opening 243 and the sixth opening 246 are formed at the same time, and the first opening 241 and the fourth opening 244 are formed in the dense area A and the sparse area B, the second opening 242 and the fifth opening 245, and the third opening 243 and the sixth opening 246 are completed in different processes, it is beneficial to reduce the impact on different processes, so that in the process of forming the fifth opening 245 in the dense area A and forming the sixth opening 246 in the sparse area B, the first source and drain doping region 221 at the bottom of the first opening 241 and the second source and drain doping region 222 at the bottom of the fourth opening 244 will not be over-etched, thereby reducing the leakage current between the first gate structure 211 and the substrate 200, and between the second gate structure 212 and the substrate 200, so that the performance of the formed semiconductor structure is better.

Referring to FIG. 15 , a conductive material is filled in the first opening 241 , the second opening 242 , and the third opening 243 to form a conductive structure 270 .

Since the third opening 243 is connected to the first opening 241 and the second opening 242 respectively, the conductive structure 270 located in the third opening 243, the first opening 241 and the second opening 242 can electrically connect the first source and drain doped region 221 and the first gate structure 221 together, thereby meeting the process requirements.

In this embodiment, the further step includes: filling the fourth opening 244 , the fifth opening 245 and the sixth opening 246 with conductive material to form the conductive structure 270 .

In this embodiment, the method for forming the conductive structure 270 includes: forming a conductive material film in the first opening 241, the second opening 242, the third opening 243, the fourth opening 244, the fifth opening 245, the sixth opening 246, and on the surface of the dielectric layer 230; planarizing the conductive material film until the surface of the dielectric layer 230 is exposed, forming the conductive structure 270 in the first opening 241, the second opening 242 and the third opening 243 on the dense area A, and forming the conductive structure 270 in the fourth opening 244, the fifth opening 245, and the sixth opening 246 on the sparse area B.

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims (22)

1. A method of forming a semiconductor structure, comprising:

Providing a substrate comprising a dense region;

Forming a plurality of first gate structures located on the substrate, a plurality of first source-drain doped regions located in the substrate and a dielectric layer located on the substrate, wherein the first gate structures are located on the dense region, the first gate structures comprise first gate layers, the substrate on two sides of each first gate structure is internally provided with first source-drain doped regions respectively, and the dielectric layer is located on the surfaces of the first gate structures and the surfaces of the first source-drain doped regions;

Forming a plurality of first openings in the dielectric layer, wherein the bottom of each first opening exposes the top surface of a first source-drain doped region;

forming a plurality of second openings in the dielectric layer, wherein the bottom of each second opening exposes a part of the surface of the top of one first gate structure;

And forming a plurality of third openings in the dielectric layer, wherein the bottoms of the third openings are higher than the top surface of the first grid layer, and the third openings are respectively communicated with the first openings and the second openings.

2. The method of forming a semiconductor structure of claim 1, wherein the second opening is formed after the first opening is formed.

3. The method of forming a semiconductor structure of claim 1, wherein the substrate further comprises a sparse region; the substrate is also provided with a plurality of second gate structures and a plurality of second source-drain doped regions positioned in the substrate, the second gate structures are positioned on the sparse regions, the second gate structures comprise second gate layers, and the substrate at two sides of each second gate structure is internally provided with a second source-drain doped region respectively;

The dielectric layer is positioned on the surface of the second grid structure and the surface of the second source-drain doped region.

4. The method of forming a semiconductor structure of claim 3, further comprising: forming a plurality of fourth openings in the dielectric layer, wherein the bottom of each fourth opening exposes the top surface of a second source-drain doped region; forming a plurality of fifth openings in the dielectric layer, wherein the bottom of each fifth opening exposes part of the surface of the top of one second grid structure, and the fourth openings and the fifth openings are mutually separated; and forming a plurality of sixth openings in the dielectric layer, wherein the bottoms of the sixth openings are higher than the top surface of the second grid layer, and the sixth openings are respectively communicated with the fourth openings and the fifth openings.

5. The method of forming a semiconductor structure of claim 4, wherein the first opening and the fourth opening are formed simultaneously; the second opening and the fifth opening are formed simultaneously; the third opening and the sixth opening are formed simultaneously.

6. The method of forming a semiconductor structure of claim 5, wherein the method of forming the first opening and the fourth opening comprises: forming a first patterning layer on the surface of the dielectric layer, wherein the first patterning layer exposes the surfaces of the dielectric layers on the first source drain doping region and the second source drain doping region; and etching the dielectric layer by taking the first patterned layer as a mask until the top surfaces of the first source drain doped region and the second source drain doped region are exposed, forming the first opening in the dense region and forming the fourth opening in the sparse region.

7. The method of forming a semiconductor structure of claim 6, wherein the method of forming the second opening and the fifth opening comprises: forming a second graphical layer on the dielectric layer, wherein the second graphical layer exposes the surfaces of the dielectric layer on the first grid structure and the second grid structure; and etching the dielectric layer by taking the second graphical layer as a mask until the top surfaces of the first grid electrode structure and the second grid electrode structure are exposed, forming the second opening in the dense region and forming the fifth opening in the sparse region.

8. The method of forming a semiconductor structure of claim 7, further comprising: forming a first planarization layer in the first opening and on the surface of the dielectric layer after forming the first opening and before forming the second opening; the second graphical layer is positioned on the surface of the first planarization layer; after the second opening is formed, the first planarization layer is removed.

9. The method of forming a semiconductor structure of claim 8, wherein a material of the first planarization layer and a material of the dielectric layer are different.

10. The method of forming a semiconductor structure of claim 9, wherein the material of the first planarization layer comprises: organic material containing carbon and oxygen.

11. The method of forming a semiconductor structure of claim 7, wherein the method of forming the third opening and the sixth opening comprises: forming a third patterning layer on the dielectric layer, wherein the third patterning layer exposes the surface of the dielectric layer between the first opening and the second opening and the surface of the dielectric layer between the fourth opening and the fifth opening; and etching the dielectric layer by taking the third graphical layer as a mask, forming the third opening in the dense region and forming the sixth opening in the sparse region.

12. The method of forming a semiconductor structure of claim 11, further comprising: forming a second planarization layer on the surfaces of the first opening, the second opening and the dielectric layer after forming the second opening and before forming the third opening; the third patterning layer is positioned on the surface of the second planarization layer; after the third opening is formed, the second planarization layer is removed.

13. The method of forming a semiconductor structure of claim 12, wherein a material of the second planarization layer and a material of the dielectric layer are different.

14. The method of forming a semiconductor structure of claim 13, wherein the material of the second planarization layer comprises: organic material containing carbon and oxygen.

15. The method of forming a semiconductor structure of claim 1, wherein the aspect ratio of the third opening ranges from 2:9 to 8:3.

16. The method of forming a semiconductor structure of claim 3, wherein a distance between adjacent first gate structures is less than a distance between adjacent second gate structures.

17. The method of claim 1, wherein the base comprises a substrate and a plurality of fins on a surface of the substrate, the first gate structure spans the plurality of fins, and the first gate structure covers a portion of top and sidewall surfaces of the fins; the first source-drain doped region is located in fin portions on two sides of the first gate structure.

18. The method of forming a semiconductor structure of claim 11, wherein the forming of the first patterned layer comprises: an extreme ultraviolet lithography process; the forming process of the second patterned layer comprises the following steps: an extreme ultraviolet lithography process; the forming process of the third patterned layer comprises the following steps: an extreme ultraviolet lithography process.

19. The method of forming a semiconductor structure of claim 1, further comprising: and filling conductive materials in the first opening, the second opening and the third opening to form a conductive structure.

20. The method of forming a semiconductor structure of claim 1, wherein the dielectric layer comprises: the semiconductor device comprises a first dielectric layer, an etching stop layer positioned on the surface of the first dielectric layer and a second dielectric layer positioned on the surface of the etching stop layer.

21. The method of forming a semiconductor structure of claim 20, wherein the first gate structure further comprises: the first barrier layer is positioned on the top surface of the first gate dielectric layer and the top surface of the first gate layer.

22. The method of forming a semiconductor structure of claim 21, wherein the forming of the first gate structure, the first source drain doped region, and the dielectric layer comprises: forming a first dummy gate structure on the substrate; forming first source-drain doped regions in the substrate at two sides of the first pseudo gate structure; forming a first dielectric layer on the substrate, wherein the first dielectric layer is positioned on the surface of the first pseudo gate structure and the surface of the first source drain doped region; removing the first dummy gate structure, and forming a first dummy gate opening in the first dielectric layer; forming a first gate dielectric layer, a first gate electrode layer positioned on the surface of the first gate dielectric layer and a first barrier layer positioned on the top surface of the first gate dielectric layer and the top surface of the first gate electrode layer in the first pseudo gate opening; forming an etching stop layer on the surfaces of the first barrier layer and the first dielectric layer; and forming the second dielectric layer on the surface of the etching stop layer.