CN113629145B - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and method of forming the same, wherein the structure comprises: the substrate is provided with a grid structure, and source and drain doped regions are respectively arranged in the substrate at two sides of the grid structure; the dielectric layer is positioned on the substrate and covers the surface of the grid structure and the surface of the source-drain doped region, and an opening exposing the top surface of the source-drain doped region is formed in the dielectric layer; a first isolation layer positioned on the surface of the side wall of the opening; and the conductive structure is positioned on the first isolation layer and on the surface of the source-drain doped region, and fills the opening. Because the first isolation layer has a certain thickness and has an isolation function, the difficulty of an etching process for forming the opening can be reduced, and meanwhile, the generation of leakage current can be effectively reduced.

Description

Semiconductor structure and method for forming the same

Technical Field

The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof.

Background Art

As the production of integrated circuits develops towards very large-scale integrated circuits, the density of their internal circuits is getting higher and higher, the number of components is increasing, and the size of devices is shrinking.

The manufacturing process of semiconductor integrated circuits is extremely complicated. It is necessary to manufacture various electronic components required for a specific circuit on a small area of silicon wafer, and it is also necessary to make appropriate internal wires between the components to form electrical connections in order to achieve the desired functions. Transistors, as the most basic semiconductor devices, are currently being widely used. The transistors include: a substrate; a gate structure located on the substrate; and source and drain doping regions located on both sides of the gate structure. In order to achieve electrical connection between the transistor and other semiconductor devices on the substrate, a large number of conductive structures need to be manufactured, such as conductive plugs or electrical interconnects located on the surface of the source and drain doping regions. The performance of these conductive structures has an important impact on the overall performance of the circuit.

However, the performance of the semiconductor structure formed by the prior art needs to be improved.

Summary of the invention

The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, a gate structure is provided on the substrate, and source and drain doping regions are respectively provided in the substrate on both sides of the gate structure; a dielectric layer located on the substrate and covering the surface of the gate structure and the surface of the source and drain doping regions, and the dielectric layer has an opening exposing the top surface of the source and drain doping regions; a first isolation layer located on the side wall surface of the opening; and a conductive structure located on the first isolation layer and on the surface of the source and drain doping regions, and the conductive structure fills the opening.

Optionally, a dimension of the first isolation layer in a direction perpendicular to the surface of the side wall of the opening ranges from 3 nanometers to 6 nanometers.

Optionally, a material of the first isolation layer is an insulating material, and the insulating material includes: silicon oxide, silicon nitride, silicon carbide, silicon boron nitride, silicon carbon nitride or silicon oxynitride.

Optionally, a dimension of the opening in a direction perpendicular to a surface of a side wall of the opening ranges from 10 nanometers to 30 nanometers.

Optionally, it further includes: a second isolation layer located on the surface of the first isolation layer, and the second isolation layer is located between the conductive structure and the first isolation layer.

Optionally, a dimension of the second isolation layer in a direction perpendicular to the surface of the sidewall of the opening ranges from 3 nanometers to 6 nanometers.

Optionally, a material of the second isolation layer is an insulating material, and the insulating material includes: silicon oxide, silicon nitride, silicon carbide, silicon boron nitride, silicon carbon nitride or silicon oxynitride.

Optionally, the conductive structure includes: an adhesion layer located on the surface of the source/drain doped region and the first isolation layer, and a conductive layer located on the surface of the adhesion layer, and the conductive layer completely fills the opening.

Optionally, the base includes a substrate and a fin located on the surface of the substrate, the gate structure spans the fin, and the gate structure is located on a portion of the top surface and sidewall surface of the fin, and the source and drain doping regions are located in the fins on both sides of the gate structure.

Optionally, a top surface of the dielectric layer is higher than a top surface of the gate structure.

Optionally, the gate structure includes: a gate dielectric layer located on the surface of the substrate, a gate layer located on the surface of the gate dielectric layer, and a barrier layer located on the top surfaces of the gate dielectric layer and the gate layer.

Optionally, the distance between adjacent gate structures ranges from 10 nanometers to 55 nanometers.

Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, having a gate structure on the substrate, and having source and drain doping regions in the substrate on both sides of the gate structure respectively; forming a dielectric layer on the substrate, and the dielectric layer covers the gate structure and the surface of the source and drain doping regions; forming an opening in the dielectric layer to expose the top surface of the source and drain doping regions; forming a first isolation layer on the side wall surface of the opening; forming a conductive structure on the first isolation layer and the surface of the source and drain doping regions, and the conductive structure fills the opening.

Optionally, the method for forming the opening includes: forming a first patterned layer on the surface of the dielectric layer, the first patterned layer exposing a portion of the surface of the dielectric layer; using the first patterned layer as a mask, etching the dielectric layer until the top surface of the source and drain doped region is exposed to form the opening.

Optionally, the method for forming the first isolation layer includes: forming an initial first isolation layer on the bottom surface and side wall surfaces of the opening, and the surface of the first patterned layer; and etching back the initial first isolation layer until the top surface of the source and drain doped regions and the surface of the first patterned layer are exposed to form the first isolation layer.

Optionally, the formation process of the initial first isolation layer includes: an atomic layer deposition process; the size of the initial first isolation layer in a direction perpendicular to the surface of the opening sidewall is in a range of 4 nanometers to 7 nanometers.

Optionally, the method further includes: after forming the first isolation layer and before forming the conductive structure, removing the first patterned layer.

Optionally, the material of the first patterned layer is different from the material of the dielectric layer; the material of the first patterned layer includes: titanium nitride, silicon nitride or silicon oxynitride, or a combination of several of them.

Optionally, the process of removing the first patterned layer includes: a wet etching process.

Optionally, the method further includes: after forming the first isolation layer and before forming the conductive structure, performing an ion implantation process on the source and drain doping regions.

Optionally, the ion implantation process includes: forming a second patterned layer on the surface of the dielectric layer, wherein the second patterned layer exposes an opening; using the second patterned layer as a mask, implanting ions into the source and drain doping regions at the bottom of the opening; and removing the second patterned layer after the ion implantation.

Optionally, the method further includes: after the ion implantation process and before forming the conductive structure, forming a second isolation layer on the surface of the first isolation layer.

Optionally, the method for forming the second isolation layer includes: forming an initial second isolation layer on the bottom surface of the opening, the surface of the first isolation layer, and the surface of the dielectric layer; etching back the initial second isolation layer until the top surface of the source and drain doped regions and the surface of the dielectric layer are exposed to form the second isolation layer.

Optionally, the formation process of the initial second isolation layer includes: an atomic layer deposition process; the size of the initial second isolation layer in a direction perpendicular to the surface of the opening sidewall is in a range of 4 nanometers to 7 nanometers.

Optionally, the method for forming the conductive structure includes: forming an adhesive film on the surface of the source/drain doped region and the first isolation layer, and on the surface of the dielectric layer; forming a conductive film on the surface of the adhesive film, and the conductive film fills the opening; flattening the adhesive film and the conductive film until the surface of the dielectric layer is exposed, so that the adhesive film forms an adhesive layer, and the conductive film forms a conductive layer, and a conductive structure is formed in the opening.

Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

In the semiconductor structure provided by the technical solution of the present invention, the surface of the side wall of the opening has a first isolation layer; the conductive structure is located on the first isolation layer. Since the first isolation layer has a certain thickness and has an isolation function, the first isolation layer occupies a certain space in the opening, so that when the distance between adjacent gate structures is small, an opening with a sufficiently large width can be formed, thereby reducing the difficulty of the etching process for forming the opening. At the same time, the first isolation layer can effectively prevent the short circuit between the conductive structure and the gate structure, effectively reduce the generation of leakage current, and make the performance of the formed semiconductor structure better.

Furthermore, a second isolation layer is formed on the surface of the first isolation layer, and the second isolation layer is located between the first isolation layer and the conductive structure. On the one hand, the second isolation layer has a certain thickness, and the second isolation layer occupies a certain space in the opening, which can make up for the material loss caused by the process after the first isolation layer is formed, thereby ensuring that the first isolation layer and the second isolation layer have a certain thickness together, so that when the distance between adjacent gate structures is small, an opening with a large enough width can be formed, thereby effectively reducing the difficulty of the etching process for forming the opening. On the other hand, the quality and surface defects of the second isolation layer material are relatively small, which is conducive to improving the morphology and performance of the conductive structure formed subsequently. In summary, the second isolation layer is conducive to improving the performance of the formed semiconductor structure.

In the method for forming a semiconductor structure provided by the technical solution of the present invention, after forming a first isolation layer on the surface of the side wall of the opening, a conductive structure is formed in the opening. Since the first isolation layer has a certain thickness and has an isolation function, the first isolation layer occupies a certain space in the opening, so that when the distance between adjacent gate structures is small, an opening with a sufficiently large width can be formed, thereby reducing the difficulty of the etching process for forming the opening. At the same time, the first isolation layer can effectively prevent short circuits between the conductive structure and the gate structure, effectively reduce the generation of leakage current, and make the performance of the formed semiconductor structure better.

Furthermore, the method for forming the semiconductor structure also includes: after the ion implantation process and before the conductive structure is formed, forming a second isolation layer on the surface of the first isolation layer. On the one hand, the second isolation layer has a certain thickness, and the second isolation layer occupies a certain space in the opening, which can make up for the material loss caused by the process after the first isolation layer is formed, thereby ensuring that the first isolation layer and the second isolation layer have a certain thickness together, so that when the distance between adjacent gate structures is small, an opening with a sufficiently large width can be formed, thereby effectively reducing the difficulty of the etching process for forming the opening. On the other hand, the quality and surface defects of the second isolation layer material are relatively small, which is conducive to improving the morphology and performance of the conductive structure formed subsequently. In summary, the second isolation layer is conducive to improving the performance of the formed semiconductor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

1 to 4 are schematic structural diagrams of various steps of a method for forming a semiconductor structure;

5 to 15 are schematic structural diagrams of various steps of a method for forming a semiconductor structure in an embodiment of the present invention.

DETAILED DESCRIPTION

First, the reasons why the performance of the existing semiconductor structure is poor are described in detail with reference to the accompanying drawings. FIG. 1 to FIG. 4 are schematic structural diagrams of various steps of a method for forming an existing semiconductor structure.

Referring to FIG. 1 , a substrate 100 is provided. A gate structure 110 is formed on the substrate 100 , and source and drain doped regions 120 are respectively formed in the substrate 100 on both sides of the gate structure 110 .

Referring to FIG. 2 , a dielectric layer 130 is formed on the substrate 100 , and the dielectric layer 130 covers the surface of the gate structure 110 and the source-drain doped region 120 .

Referring to FIG. 3 , an opening 140 is formed in the dielectric layer 130 to expose the top surface of the source/drain doped region 120 .

Referring to FIG. 4 , a conductive structure 150 is formed in the opening 140 .

In the above method, the method for forming the opening 140 includes: forming a patterned layer on the surface of the dielectric layer 130, wherein the patterned layer exposes a portion of the surface of the dielectric layer 130; using the patterned layer as a mask, etching the dielectric layer 130 until the surface of the source and drain doped region 120 is exposed.

However, with the development of semiconductor technology, the integration of semiconductors is getting higher and higher, and the distance between adjacent devices is getting smaller and smaller. In the process of etching the dielectric layer 130 to form the opening 140, it is easy to cause etching damage to the material of the gate structure 110, thereby causing a short circuit between the conductive structure 150 subsequently formed in the opening 140 and the gate structure 110, thereby generating leakage current.

In order to solve the above problem, by reducing the size of the opening 140, the distance between the opening 140 and the gate structure 110 can be increased, thereby reducing the possibility of short circuit between the conductive structure 150 and the gate structure 110 formed in the opening 140. However, forming the opening 140 with a further reduced size exceeds the limit of the existing photolithography process, increases the difficulty of etching to form the opening 140, and makes the morphology of the formed opening 140 poor, and even fails to form the opening 140 that exposes the top surface of the source-drain doped region 120, resulting in poor performance of the formed semiconductor structure.

In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, wherein after forming a first isolation layer on the surface of the sidewall of the opening, a conductive structure is formed on the first isolation layer and on the surface of the source and drain doping regions, and the conductive structure fills the opening. Since the first isolation layer has a certain thickness and the first isolation layer has an isolation function, the difficulty of the etching process for forming the opening can be reduced while effectively reducing the generation of leakage current.

In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

It should be noted that the “surface” in this specification is used to describe the relative position relationship in space and is not limited to whether there is direct contact.

5 to 15 are schematic structural diagrams of various steps of a method for forming a semiconductor structure in an embodiment of the present invention.

Referring to FIG. 5 , a substrate 200 is provided. A gate structure 210 is formed on the substrate 200 , and source and drain doped regions 220 are respectively formed in the substrate 200 on both sides of the gate structure 210 .

In this embodiment, the base 200 includes a substrate and a fin located on the surface of the substrate, the gate structure 210 spans the fin, and the gate structure 210 is located on the top surface and sidewall surface of a portion of the fin, and the source and drain doped regions 220 are located in the fins on both sides of the gate structure 210.

In other embodiments, the substrate has no fins thereon.

In this embodiment, the method for forming the base 200 includes: providing an initial substrate (not shown); the initial substrate has a mask layer, and the mask layer exposes a portion of the surface of the initial substrate; using the mask layer as a mask, etching the initial substrate to form a substrate and a fin located on the surface of the substrate.

In this embodiment, the material of the initial substrate is silicon. Accordingly, the material of the substrate and the fin is silicon.

In other embodiments, the material of the initial substrate includes: germanium, silicon germanium, silicon on insulator or germanium on insulator. Correspondingly, the material of the substrate includes: germanium, silicon germanium, silicon on insulator or germanium on insulator. The material of the fin includes: germanium, silicon germanium, silicon on insulator or germanium on insulator.

The distance between adjacent gate structures 210 ranges from 10 nanometers to 55 nanometers.

The method for forming the gate structure 210 and the source-drain doped region 220 includes: forming a dummy gate structure (not shown in the figure) on the substrate 200; forming source-drain doped regions 220 in the substrate 200 on both sides of the dummy gate structure; forming a first dielectric layer (not shown in the figure) on the substrate 200, the first dielectric layer being located on the surface of the dummy gate structure and the surface of the source-drain doped region 220; removing the dummy gate structure, forming a dummy gate opening in the first dielectric layer; and forming a gate structure 210 in the dummy gate opening.

In this embodiment, the gate structure 210 includes: a gate dielectric layer (not shown in the figure) located on the surface of the substrate 200; a gate layer (not shown in the figure) located on the surface of the gate dielectric layer, and a blocking layer (not shown in the figure) located on the top surface of the gate dielectric layer and the top surface of the gate layer.

In this embodiment, the gate dielectric layer is located on the sidewalls and bottom surfaces of the dummy gate opening.

In this embodiment, the gate structure 210 further includes: sidewalls (not shown in the figure) located on the sidewall surfaces of the barrier layer and the gate dielectric layer.

The material of the gate dielectric layer is a high-K (K greater than 3.9) dielectric material, including: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide. In this embodiment, the material of the gate dielectric layer is hafnium oxide.

The material of the gate layer includes: one or more combinations of copper, tungsten, aluminum, titanium, nickel, titanium nitride and tantalum nitride. In this embodiment, the material of the gate layer is tungsten.

The barrier layer is used to protect the surfaces of the gate layer and the gate dielectric layer, reduce the impact of subsequent processes, and is beneficial to the morphology and performance of the gate structure 210 .

The material of the barrier layer includes silicon nitride, silicon oxynitride or titanium dioxide.

It should be noted that, in this embodiment, the top surface of the first dielectric layer is flush with the top surface of the gate structure 210 and is a part of the subsequent dielectric layer.

Referring to FIG. 6 , a dielectric layer 230 is formed on the substrate 200 , and the dielectric layer 230 covers the surface of the gate structure 210 and the source-drain doped region 220 .

The dielectric layer 230 has the following functions: on the one hand, it provides support for the subsequent formation of a conductive structure; on the other hand, it is used to electrically isolate different devices.

The material of the dielectric layer 230 includes silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

In this embodiment, the material of the dielectric layer 230 is silicon oxide.

In this embodiment, the dielectric layer 230 includes: a first dielectric layer (not shown in the figure) and a second dielectric layer (not shown in the figure) located on the surface of the first dielectric layer, the top surface of the first dielectric layer is flush with the top surface of the gate structure 210, and the top surface of the second dielectric layer is higher than the top surface of the gate structure 210.

Specifically, in this embodiment, a second dielectric layer is formed on the surface of the first dielectric layer on the substrate 200 , thereby forming a dielectric layer 230 on the substrate 200 .

The top surface of the dielectric layer 230 is higher than the top surface of the gate structure 210 .

Next, an opening is formed in the dielectric layer 230 to expose the top surface of the source-drain doped region 220 . Please refer to FIG. 7 to FIG. 8 for the specific process of forming the opening.

Referring to FIG. 7 , a first patterned layer 240 is formed on the surface of the dielectric layer 230 , and the first patterned layer 240 exposes a portion of the surface of the dielectric layer 230 .

The first patterned layer 240 is used as a mask for subsequently forming openings.

The material of the first patterned layer 240 is different from that of the dielectric layer 230. The material of the first patterned layer includes: titanium nitride, silicon nitride or silicon oxynitride or a combination thereof. In this embodiment, the material of the first patterned layer 240 is titanium nitride.

The method for forming the first patterned layer 240 includes: forming an initial first patterned layer (not shown in the figure) on the surface of the dielectric layer 230; forming a mask layer (not shown in the figure) on the surface of the initial first patterned layer; using the mask layer as a mask, etching the initial first patterned layer to form the first patterned layer 240, wherein the first patterned layer 240 has a pattern.

In this embodiment, the material of the mask layer is photoresist.

Referring to FIG. 8 , the dielectric layer 230 is etched using the first patterned layer 240 as a mask until the top surface of the source/drain doped region 220 is exposed, thereby forming the opening 250 .

The opening 250 provides space for subsequently forming a conductive structure.

The size of the opening 250 along a direction perpendicular to the sidewall surface of the opening 250 ranges from 10 nanometers to 30 nanometers.

The process of etching the dielectric layer 230 includes: a dry etching process and a wet etching process, or a combination of the two.

In this embodiment, the process of etching the dielectric layer 230 is a dry etching process.

Next, after the opening 250 is formed, a first isolation layer is formed on the sidewall surface of the opening 250 . For the specific process of forming the first isolation layer, please refer to FIG. 9 to FIG. 10 .

Referring to FIG. 9 , an initial first isolation layer 251 is formed on the bottom surface and sidewall surface of the opening 250 , and on the surface of the first patterned layer 240 .

The initial first isolation layer 251 is used to provide material for subsequently forming a first isolation layer.

The material of the initial first isolation layer 251 is an insulating material, and the insulating material includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride or silicon oxynitride.

In this embodiment, the material of the initial first isolation layer 251 is silicon nitride.

The formation process of the initial first isolation layer 251 includes: atomic layer deposition process, chemical vapor deposition process or physical vapor deposition process.

In this embodiment, the initial first isolation layer 251 is formed by an atomic layer deposition process.

The initial first isolation layer 251 formed by the atomic layer deposition process has high density, which is beneficial to improving the isolation effect and blocking effect of the subsequently formed first isolation layer. At the same time, the initial first isolation layer 251 has good filling properties, which is beneficial to filling the surface defects on the side walls of the opening 250 and avoiding short circuits between the subsequently formed conductive structure and the gate structure 210.

The size of the initial first isolation layer 251 along the direction perpendicular to the sidewall surface of the opening ranges from 4 nanometers to 7 nanometers.

The reason for selecting the size range is that, if the size is greater than 7 nanometers, the thickness of the initial first isolation layer 251 is too large, and thus the thickness of the first isolation layer formed by the initial first isolation layer 251 is too large, thereby occupying too much space in the opening 250, making the size of the subsequent conductive structure filled in the opening 250 too small, resulting in excessive contact resistance, which is not conducive to the performance of the formed semiconductor structure; if the size is less than 4 nanometers, the initial first isolation layer 251 is too thin, and thus the thickness of the first isolation layer formed by the initial first isolation layer 251 is too thin, and cannot fully play an isolation and blocking role in the subsequent process, thereby causing a short circuit between the conductive structure and the gate structure 210 subsequently formed in the opening 250, resulting in the performance of the formed semiconductor structure still being poor.

Referring to FIG. 10 , the initial first isolation layer 251 is etched back until the top surface of the source/drain doped region 220 and the surface of the first patterned layer 240 are exposed, thereby forming the first isolation layer 252 .

The process of etching back the initial first isolation layer 251 includes: one of a dry etching process and a wet etching process or a combination of the two.

In this embodiment, the process of etching back the first isolation layer 251 is an anisotropic dry etching process.

The first isolation layer 252 is formed by etching back the initial first isolation layer 251. Accordingly, the material of the first isolation layer 252 is an insulating material. In this embodiment, the material of the first isolation layer 252 is silicon nitride.

Since the first isolation layer 252 has a certain thickness and has an isolation function, the first isolation layer 252 occupies a certain space in the opening, so that when the distance between adjacent gate structures 210 is small, an opening 250 with a sufficiently large width can be formed, thereby reducing the difficulty of the etching process for forming the opening 250. At the same time, the first isolation layer 252 can effectively prevent a short circuit between the subsequently formed conductive structure and the gate structure 210, effectively reduce the generation of leakage current, and make the formed semiconductor structure have better performance.

Referring to FIG. 11 , after the first isolation layer 252 is formed, the first patterned layer 240 is removed.

In this embodiment, the process for removing the first patterned layer 240 is a wet etching process, and the parameters of the wet etching process include: the etching solution used includes sulfuric acid solution and hydrogen peroxide, the volume ratio of the sulfuric acid solution and hydrogen peroxide is 4.5:1 to 10.5:1, and the temperature is 25 degrees Celsius to 140 degrees Celsius.

Since the side wall surface of the opening 250 has the first isolation layer 252, the first isolation layer 252 can protect the side wall surface of the opening 250, thereby effectively reducing the etching loss caused to the side wall of the opening and the gate structure 210 adjacent to the opening 250, thereby preventing the subsequent short circuit between the conductive structure formed in the opening and the gate structure 210, effectively reducing the generation of leakage current, and making the performance of the formed semiconductor structure better.

It should be noted that the first isolation layer 252 will be subjected to certain etching losses during the process of removing the first patterned layer 240 , so that the thickness of the first isolation layer 252 is reduced and the surface of the first isolation layer 252 has certain defects.

Please refer to FIG. 12 , after forming the first isolation layer 252 , an ion implantation process is performed on the source/drain doping region 220 .

The ion implantation process is used to reduce the contact resistance between the subsequently formed conductive structure and the source/drain doped region 220 .

In this embodiment, the ion implantation process is performed after the first patterned layer 240 is removed.

In this embodiment, the method of the ion implantation process includes: forming a second patterned layer (not shown in the figure) on the surface of the dielectric layer 230, wherein the second patterned layer exposes the opening 250; using the second patterned layer as a mask, ion implanting the source/drain doping region 220 at the bottom of the opening 240; after the ion implantation, removing the second patterned layer.

The material of the second patterned layer is different from the material of the dielectric layer 230 ; the material of the second patterned layer includes: titanium nitride, silicon nitride or silicon oxynitride, or a combination of several of them.

In this embodiment, the material of the second patterned layer is titanium nitride.

The process of removing the second patterned layer includes: a wet etching process.

It should be noted that, during the process of removing the second patterned layer, the first isolation layer 252 will be subjected to a certain amount of etching loss, so that the thickness of the first isolation layer 252 is reduced and certain defects are generated on the surface of the first isolation layer 252 .

It should be noted that the thickness refers to the dimension in a direction perpendicular to the side wall of the opening 250 .

Next, a second isolation layer is formed on the surface of the first isolation layer 252 . For the specific process of forming the second isolation layer, please refer to FIG. 13 and FIG. 14 .

Referring to FIG. 13 , an initial second isolation layer 261 is formed on the bottom surface of the opening 250 , the surface of the first isolation layer 252 , and the surface of the dielectric layer 230 .

The initial second isolation layer 261 provides material for subsequently forming a second isolation layer.

The formation process of the initial second isolation layer 261 includes: an atomic layer deposition process.

The formation process of the initial second isolation layer 261 includes: atomic layer deposition process, chemical vapor deposition process or physical vapor deposition process.

In this embodiment, the initial second isolation layer 261 is formed by an atomic layer deposition process.

By adopting the atomic layer deposition process, on the one hand, the initial second isolation layer 261 formed has a higher density, which is beneficial to improving the isolation effect and blocking effect of the subsequently formed second isolation layer. On the other hand, the initial second isolation layer 261 has a better morphology and fewer surface defects, which is beneficial to improving the material quality of the conductive structure subsequently formed on the surface of the second isolation layer, thereby benefiting the electrical properties of the conductive structure.

The size of the initial second isolation layer 261 along a direction perpendicular to the sidewall surface of the opening 250 ranges from 4 nanometers to 7 nanometers.

The reason for selecting the size range is that, if the size is greater than 7 nanometers, the thickness of the initial second isolation layer 261 is too large, and thus the thickness of the second isolation layer formed by the initial second isolation layer 261 is too large, so that the space occupied by the opening 250 is too large, and the size of the subsequent conductive structure filled in the opening 250 is too small, resulting in excessive contact resistance, which is not conducive to the performance of the formed semiconductor structure; if the size is less than 4 nanometers, the initial second isolation layer 261 is too thin, and thus the thickness of the second isolation layer formed by the initial second isolation layer 261 is relatively thin, which cannot make up for the loss of the first isolation layer 252 material, and the surface morphology and quality are poor, which is not conducive to the morphology of the subsequent conductive structure, resulting in the formed semiconductor structure The performance is still poor.

Referring to FIG. 14 , the initial second isolation layer 261 is etched back until the top surface of the source/drain doped region 220 and the surface of the dielectric layer 230 are exposed, thereby forming the second isolation layer 262 .

The process of etching back the initial second isolation layer 261 includes: one of a dry etching process and a wet etching process or a combination of the two.

In this embodiment, the process of etching back the initial second isolation layer 261 is an anisotropic dry etching process.

The second isolation layer 262 is formed by etching back the initial second isolation layer 261 . Accordingly, the material of the second isolation layer 262 is an insulating material.

In this embodiment, the second isolation layer 262 and the first isolation layer 261 are made of the same material, which is silicon nitride.

In other embodiments, the material of the second isolation layer and the material of the first isolation layer may be different.

A second isolation layer 262 is formed on the surface of the first isolation layer 252. On the one hand, the second isolation layer 262 has a certain thickness, and the second isolation layer 262 occupies a certain space in the opening, which can make up for the material loss caused by the process after the first isolation layer 252 is formed, thereby ensuring that the first isolation layer 252 and the second isolation layer 262 have a certain thickness together, so that when the distance between adjacent gate structures 210 is small, an opening 250 with a sufficiently large width can be formed, thereby effectively reducing the difficulty of the etching process for forming the opening 250. On the other hand, the quality of the material of the second isolation layer 262 and the surface defects are relatively small, which is conducive to improving the morphology and performance of the conductive structure formed subsequently, and further conducive to improving the performance of the formed semiconductor structure.

Referring to FIG. 15 , a conductive structure 270 is formed on the first isolation layer 252 and on the surface of the source/drain doped region 220 , and the conductive structure 270 completely fills the opening 250 .

The method for forming the conductive structure 270 includes: forming an adhesive film (not shown in the figure) on the surface of the source/drain doped region 220 and the first isolation layer 252, and on the surface of the dielectric layer 230; forming a conductive film (not shown in the figure) on the surface of the adhesive film, and the conductive film fills the opening 250; planarizing the adhesive film and the conductive film until the surface of the dielectric layer 230 is exposed, so that the adhesive film forms an adhesive layer, and the conductive film forms a conductive layer, and a conductive structure is formed in the opening 250.

In this embodiment, a second isolation layer 262 is disposed on the surface of the first isolation layer 252 . The conductive structure 270 is located on the surface of the second isolation layer 262 and the surface of the source-drain doped region 220 and fills the opening 250 .

Correspondingly, an embodiment of the present invention also provides a semiconductor structure formed by the above method, please continue to refer to Figure 15, including: a substrate 200, the substrate 200 has a gate structure 210, and the substrate 200 on both sides of the gate structure 210 has source and drain doping regions 220 respectively; a dielectric layer 230 located on the substrate 200 covering the surface of the gate structure 210 and the surface of the source and drain doping region 220, and the dielectric layer 230 has an opening 250 exposing the top surface of the source and drain doping region 220; a first isolation layer 252 located on the side wall surface of the opening 250; a conductive structure 270 located on the first isolation layer 252 and the surface of the source and drain doping region 220, and the conductive structure 270 fills the opening 250.

The sidewall surface of the opening 250 has a first isolation layer 252; the conductive structure 270 is located on the first isolation layer 252. Since the first isolation layer 252 has a certain thickness and has an isolation function, the first isolation layer 252 occupies a certain space in the opening 250, so that when the distance between adjacent gate structures 210 is small, an opening 250 with a sufficiently large width can be formed, thereby reducing the difficulty of the etching process for forming the opening 250. At the same time, the first isolation layer 252 can effectively prevent the short circuit between the conductive structure 270 and the gate structure 210, effectively reduce the generation of leakage current, and make the performance of the formed semiconductor structure better.

The following is a detailed description with reference to the accompanying drawings.

In this embodiment, the base 200 includes a substrate and a fin located on the surface of the substrate, the gate structure 210 spans the fin, and the gate structure 210 is located on the top surface and sidewall surface of a portion of the fin, and the source and drain doped regions 220 are located in the fins on both sides of the gate structure 210.

The size of the first isolation layer 252 along the direction perpendicular to the sidewall surface of the opening 250 ranges from 3 nanometers to 6 nanometers.

The material of the first isolation layer 252 is an insulating material, and the insulating material includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide, or silicon nitride oxide.

The size of the opening 250 along a direction perpendicular to the sidewall surface of the opening 250 ranges from 10 nanometers to 30 nanometers.

The conductive structure 270 includes: an adhesion layer (not shown in the figure) located on the surface of the source/drain doped region 220 and the first isolation layer 252, and a conductive layer (not shown in the figure) located on the surface of the adhesion layer, and the conductive layer fills the opening.

The semiconductor structure further includes: a second isolation layer 262 located on a surface of the first isolation layer 252 , and the second isolation layer 262 is located between the conductive structure 270 and the first isolation layer 252 .

A second isolation layer 262 is formed on the surface of the first isolation layer 252, and the second isolation layer 262 is located between the first isolation layer 252 and the conductive structure 270. On the one hand, the second isolation layer 262 has a certain thickness, and the second isolation layer 262 occupies a certain space in the opening 250, which can make up for the material loss caused by the process after the first isolation layer 252 is formed, thereby ensuring that the first isolation layer 252 and the second isolation layer 262 have a certain thickness together, so that when the distance between adjacent gate structures 210 is small, an opening 250 with a sufficiently large width can be formed, thereby effectively reducing the difficulty of the etching process for forming the opening 250. On the other hand, the quality of the material of the second isolation layer 262 and the surface defects are relatively small, which is conducive to improving the morphology and performance of the conductive structure formed subsequently. In summary, the second isolation layer is conducive to improving the performance of the formed semiconductor structure.

The size of the second isolation layer 262 along a direction perpendicular to the sidewall surface of the opening 250 ranges from 3 nanometers to 6 nanometers.

The material of the second isolation layer 262 is an insulating material, and the insulating material includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide, or silicon nitride oxide.

In this embodiment, the conductive structure 270 is located on the surface of the source/drain doped region 220 and the surface of the second isolation layer 262 , and completely fills the opening 250 .

The top surface of the dielectric layer 230 is higher than the top surface of the gate structure 210 .

The gate structure 210 includes: a gate dielectric layer (not shown in the figure) located on the surface of the substrate 200, a gate layer (not shown in the figure) located on the surface of the gate dielectric layer, and a barrier layer (not shown in the figure) located on the top surface of the gate dielectric layer and the top surface of the gate layer.

The distance between adjacent gate structures 210 ranges from 10 nanometers to 55 nanometers.

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims (22)

1. A semiconductor structure, comprising: A substrate, wherein the substrate has a gate structure, and the substrate at both sides of the gate structure has source and drain doping regions respectively; A dielectric layer located on the substrate and covering the surface of the gate structure and the surface of the source-drain doped region, wherein the dielectric layer has an opening exposing the top surface of the source-drain doped region; A first isolation layer located on the side wall surface of the opening; A conductive structure located on the first isolation layer and on the surface of the source-drain doped region, and the conductive structure completely fills the opening; A second isolation layer is located on the surface of the first isolation layer, and the second isolation layer is located between the conductive structure and the first isolation layer, and the second isolation layer is formed after an ion implantation process is performed on the source and drain doping regions. 2 . The semiconductor structure according to claim 1 , wherein a dimension of the first isolation layer in a direction perpendicular to a surface of a sidewall of the opening ranges from 3 nanometers to 6 nanometers. 3 . The semiconductor structure according to claim 1 , wherein the material of the first isolation layer is an insulating material, and the insulating material comprises silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide. 4 . The semiconductor structure according to claim 1 , wherein a dimension of the opening in a direction perpendicular to a surface of a sidewall of the opening ranges from 10 nanometers to 30 nanometers. 5 . The semiconductor structure according to claim 1 , wherein a dimension of the second isolation layer in a direction perpendicular to a surface of a sidewall of the opening ranges from 3 nanometers to 6 nanometers. 6 . The semiconductor structure according to claim 1 , wherein a material of the second isolation layer is an insulating material, and the insulating material comprises silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide, or silicon nitride oxide. 7. The semiconductor structure according to claim 1 is characterized in that the conductive structure comprises: an adhesion layer located on the surface of the source and drain doped regions and the first isolation layer, and a conductive layer located on the surface of the adhesion layer, and the conductive layer completely fills the opening. 8. The semiconductor structure as described in claim 1 is characterized in that the base includes a substrate and a fin located on the surface of the substrate, the gate structure spans the fin, and the gate structure is located on a portion of the top surface and sidewall surface of the fin, and the source and drain doping regions are located in the fins on both sides of the gate structure. 9 . The semiconductor structure according to claim 1 , wherein a top surface of the dielectric layer is higher than a top surface of the gate structure. 10. The semiconductor structure according to claim 1, wherein the gate structure comprises: a gate dielectric layer located on a substrate surface, a gate layer located on a gate dielectric layer surface, and a barrier layer located on top surfaces of the gate dielectric layer and the gate layer. 11 . The semiconductor structure according to claim 1 , wherein a distance between adjacent gate structures ranges from 10 nanometers to 55 nanometers. 12. A method for forming a semiconductor structure, comprising: Providing a substrate, wherein the substrate has a gate structure, and the substrate at both sides of the gate structure has source and drain doping regions respectively; Forming a dielectric layer on the substrate, wherein the dielectric layer covers the gate structure and the surface of the source and drain doped regions; forming an opening in the dielectric layer to expose the top surface of the source and drain doped regions; forming a first isolation layer on the side wall surface of the opening; After forming the first isolation layer, performing an ion implantation process on the source-drain doping region; After the ion implantation process, forming a second isolation layer on the surface of the first isolation layer; A conductive structure is formed on the second isolation layer and on the surface of the source-drain doped region, and the conductive structure completely fills the opening. 13. The method for forming a semiconductor structure as described in claim 12 is characterized in that the method for forming the opening comprises: forming a first patterned layer on the surface of the dielectric layer, the first patterned layer exposing a portion of the surface of the dielectric layer; using the first patterned layer as a mask, etching the dielectric layer until the top surface of the source and drain doped regions is exposed to form the opening. 14. The method for forming a semiconductor structure as described in claim 13 is characterized in that the method for forming the first isolation layer comprises: forming an initial first isolation layer on the bottom surface and side wall surface of the opening, and the surface of the first patterned layer; etching back the initial first isolation layer until the top surface of the source and drain doped regions and the surface of the first patterned layer are exposed to form the first isolation layer. 15. The method for forming a semiconductor structure as described in claim 14 is characterized in that the formation process of the initial first isolation layer comprises: an atomic layer deposition process; the size of the initial first isolation layer in a direction perpendicular to the surface of the opening side wall ranges from 4 nanometers to 7 nanometers. 16 . The method for forming a semiconductor structure according to claim 13 , further comprising: removing the first patterned layer after forming the first isolation layer and before forming the conductive structure. 17. The method for forming a semiconductor structure according to claim 16, wherein the material of the first patterned layer is different from the material of the dielectric layer; the material of the first patterned layer comprises: one or a combination of titanium nitride, silicon nitride or silicon oxynitride. 18 . The method for forming a semiconductor structure according to claim 17 , wherein the process of removing the first patterned layer comprises: a wet etching process. 19. The method for forming a semiconductor structure as described in claim 12 is characterized in that the ion implantation process comprises: forming a second patterned layer on the surface of the dielectric layer, wherein the second patterned layer exposes an opening; using the second patterned layer as a mask, ion implanting the source and drain doping regions at the bottom of the opening; and removing the second patterned layer after the ion implantation. 20. The method for forming a semiconductor structure as described in claim 12 is characterized in that the method for forming the second isolation layer comprises: forming an initial second isolation layer on the bottom surface of the opening, the surface of the first isolation layer, and the surface of the dielectric layer; etching back the initial second isolation layer until the top surface of the source and drain doped regions and the surface of the dielectric layer are exposed to form the second isolation layer. 21. The method for forming a semiconductor structure as described in claim 20 is characterized in that the formation process of the initial second isolation layer comprises: an atomic layer deposition process; the size of the initial second isolation layer in a direction perpendicular to the surface of the opening side wall ranges from 4 nanometers to 7 nanometers. 22. The method for forming a semiconductor structure as described in claim 12 is characterized in that the method for forming a conductive structure comprises: forming an adhesive film on the surface of the source and drain doping region and the first isolation layer, and on the surface of the dielectric layer; forming a conductive film on the surface of the adhesive film, and the conductive film fills the opening; flattening the adhesive film and the conductive film until the surface of the dielectric layer is exposed, so that the adhesive film forms an adhesive layer, and the conductive film forms a conductive layer, and a conductive structure is formed in the opening.