CN102263062B - Method for forming side walls of multiple-unit semiconductor device - Google Patents
Method for forming side walls of multiple-unit semiconductor device Download PDFInfo
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- CN102263062B CN102263062B CN 201010187417 CN201010187417A CN102263062B CN 102263062 B CN102263062 B CN 102263062B CN 201010187417 CN201010187417 CN 201010187417 CN 201010187417 A CN201010187417 A CN 201010187417A CN 102263062 B CN102263062 B CN 102263062B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000001020 plasma etching Methods 0.000 claims abstract description 32
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000005530 etching Methods 0.000 description 28
- 239000000758 substrate Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
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- 229910052760 oxygen Inorganic materials 0.000 description 1
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Abstract
The invention provides a method for forming side walls of a multiple-unit semiconductor device. The method comprises the following steps: providing the multiple-unit semiconductor device without side walls, wherein the multiple-unit semiconductor device at least comprises a first component area and a second component area, and the thicknesses of grid medium layers of transistors in each component area are different; covering and depositing an insulating medium layer on the surface of each component area of the multiple-unit semiconductor device; carrying out first plasma etching on the insulating medium layer in a vertical direction, thus a first side wall is formed in the first component area; forming a mask layer on the surface of the first component area; and carrying out second plasma etching on the insulating medium layer on the surface of the second component area in the vertical direction, thus a second side wall is formed in the second component area.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly be integrated with the multiple-unit semiconductor device sidewall formation method of low pressure, high voltage device.
Background technology
Development along with semiconductor technology, in integrated circuit fabrication process, the multiple-unit semiconductor device that is integrated with high pressure, low voltage component is increasingly common, difference according to environment for use and condition of work, the structure of high pressure and low voltage component also has larger difference, and for example the transistor gate oxide thickness of general low voltage component exists
Between, and high voltage device is breakdown for preventing owing to will bear larger threshold voltage, its gate oxide thickness in addition
More than.
In the existing multiple-unit semiconductor device, when forming the transistor sidewall, adopt overall etching technics.I.e. no matter low voltage component or the equal sidewall moulding of high voltage device, Fig. 1 to figure be the sidewall formation method schematic diagram of existing multiple-unit semiconductor device.
As shown in Figure 1, provide the multiple-unit semiconductor device that not yet forms sidewall, described multiple-unit semiconductor device comprises low voltage component district I and high voltage device district II, and wherein the thickness of transistorized thin grid oxide layer 100 is among the low voltage component district I
And the thickness of transistorized thick grid oxide layer 101 is among the high voltage device district II
A wherein side of described thick grid oxide layer 101 is also by selective oxidation technology (LOCOS), and the selective oxidation that carries out is grown, and thickness reaches
As shown in Figure 2, at the surface coverage deposition insulating medium layer 200 of multiple-unit semiconductor device, described insulating medium layer 200 can be silicon nitride or silica etc.
As shown in Figure 3, in the vertical direction described insulating medium layer 200 is adopted plasma etching, because vertical etching speed is greater than the etching speed of side direction, thus the vertical interface formation sidewall 201 of transistor gate in low voltage component district I and high voltage device district II respectively.
There are the following problems for above-mentioned existing overall sidewall forming processes: because transistorized grid oxide layer difference in thickness is larger among low voltage component district I and the high voltage device district II, cause the size difference of grid also larger, therefore deposit and carry out again etching behind the insulating medium layer when forming sidewall, be difficult to form synchronously sidewall, have following two kinds of extreme cases:
As shown in Figure 4, etch amount control is more when supposing overall sidewall etching, can access the transistor sidewall 201 among the desirable high voltage device district II, and with respect to low voltage component district I, more etch amount produces the over etching effect, with the surface of source-drain area in the damage low voltage component transistor substrate, cause junction leakage.
As shown in Figure 5, etch amount control is lower when supposing overall sidewall etching, can access the transistor sidewall 201 among the desirable low voltage component district I, and with respect to high voltage device district I, less etch amount will cause the insulating medium layer of source-drain area remained on surface in its transistor substrate partially thick, so that follow-up source is when leaking Implantation, and the ion dose step-down of injection, the degree of depth shoals, and further causes transistorized conducting resistance to uprise.
Under the restriction of above-mentioned two kinds of extreme conditions, the sidewall formation method of existing multiple-unit semiconductor device, its process window is very little, is difficult to realize the desired sidewall effect that obtains of Fig. 3, and technique is wayward, has a strong impact on the quality of product, in the urgent need to improving.
Summary of the invention
The object of the present invention is to provide a kind of sidewall formation method of multiple-unit semiconductor device, so that the components and parts of different structure size are regional, form respectively desirable separately sidewall, improve the quality of product.
For addressing the above problem, the sidewall formation method of multiple-unit semiconductor device of the present invention comprises:
The multiple-unit semiconductor device that does not form sidewall is provided, and described multiple-unit semiconductor device comprises the first element region and the second element region at least, and transistorized gate dielectric layer thickness is different in each element region;
Surface coverage deposition insulating medium layer at described each element region of multiple-unit semiconductor device;
In vertical direction described insulating medium layer is carried out the first plasma etching, so that form the first side wall in the first element region;
Surface at the first element region forms mask layer;
In vertical direction the described insulating medium layer that is positioned at the second element region surface is carried out the second plasma etching, so that form the second sidewall in the second element region.
Wherein, in described the first element region transistorized gate dielectric layer thickness less than transistorized gate dielectric layer in the second element region.
Optionally, described insulating medium layer material is silica or silicon nitride.The employing chemical vapour deposition (CVD) forms.
Described insulating medium layer is carried out the first plasma etching, until expose in the first element region till the transistorized source-drain area surface.
Optionally, described mask layer material is photoresist.
Described the insulating medium layer that is positioned at the second element region surface is carried out the second plasma etching, until expose in the second element region till the transistorized source-drain area surface.
Described formation method also comprises the step of the mask layer of removing the first element region surface.
Compared with prior art, the present invention has the following advantages: in different components and parts zone, grid size is the difference of gate dielectric layer thickness especially, adopts the mode of multiple etching, and subregion forms corresponding sidewall.Accurately control the size of etch amount, thereby guarantee the product quality of multiple-unit semiconductor device.Avoid the extreme phenomenon that exists in the overall etching, had larger process window, easy to implement.
Description of drawings
Fig. 1 to Fig. 3 is the sidewall formation method schematic diagram of existing multiple-unit semiconductor device;
Fig. 4 and Fig. 5 are two kinds of failure conditions schematic diagrames of existing sidewall formation method;
Fig. 6 is that the sidewall of multiple-unit semiconductor device of the present invention forms the method flow schematic diagram;
Fig. 7 to Figure 12 is a specific embodiment schematic diagram of sidewall formation method of the present invention.
Embodiment
The sidewall formation method of existing multiple-unit semiconductor device adopts overall sidewall etching, is easy to be subject to the grid oxygen size restrictions in different components and parts zone, and produces the situation of over etching or etching deficiency.The present invention adopts the method for substep subregion etching, solves the unmanageable problem of above-mentioned etch amount, thereby in each components and parts zone, forms required separately desirable sidewall.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
With reference to shown in Figure 6, the sidewall formation method of multiple-unit semiconductor device of the present invention, basic step comprises:
S1, provide the multiple-unit semiconductor device that does not form sidewall, described multiple-unit semiconductor device to comprise at least the first element region and the second element region, and transistorized gate dielectric layer thickness is different in each element region;
Wherein, it is relatively thin to define in the first element region transistorized gate dielectric layer thickness, also is that the grid structure size is less.In addition, in existing MOS technique, gate dielectric layer is not to aim at etching of disposable while of gate electrode sometimes, and therefore described gate dielectric layer also may be overlying on transistorized source-drain area undetermined surface, and removes in the lump in follow-up sidewall etching.
S2, at the surface coverage of described each element region of multiple-unit semiconductor device deposition insulating medium layer;
Because the difference of transistorized grid structure size in each element region, the relative thickness of described insulating medium layer when covering deposition also may be different.Described insulating medium layer is used to form sidewall, therefore should select its material according to concrete needs.Common sidewall material comprises silicon nitride and silica etc.
S3, in vertical direction described insulating medium layer is carried out the first plasma etching, so that form the first side wall in the first element region;
Wherein, described the first plasma etching will carry out on the surface of whole multiple-unit semiconductor device, because transistorized gate dielectric layer thickness is the thinnest in the first element region, the grid structure size is minimum, therefore in the first plasma etching process, the silicon face that should expose at first source-drain area, and form the first side wall, so whether the first plasma etching should expose for stopping foundation according to the silicon face in source transistor drain region in the first element region.
S4, form mask layer on the surface of the first element region;
Because the size of element region is larger, for reducing cost, to enhance productivity, the mode that can directly adopt photoresist to smear and expose only forms mask on the surface of the first element region that forms desirable sidewall.
S5, in vertical direction the described insulating medium layer that is positioned at the second element region surface is carried out the second plasma etching, so that form the second sidewall in the second element region.
Because the surface of the first element region is formed with the mask layer of protection, therefore described the second plasma etching only exerts an influence to the second element region.According to aforementioned theory, when the first plasma etching finished, the surface of the second element region is should be also residual thicker insulating medium layer or gate dielectric layer.Whether described the second plasma etching plays the effect that further etching is adjusted, should expose according to the silicon face in source transistor drain region in the second element region for stopping foundation, thereby further form the second required sidewall.
Through above-mentioned basic step, each element region will obtain desirable separately sidewall, and avoid the situation of over etching or etching deficiency.Except above-mentioned steps, also should comprise the conventional steps such as mask layer of removing the element region surface.
Below in conjunction with specific embodiment, the sidewall formation method of multiple-unit semiconductor device of the present invention is described further.
As shown in Figure 7, at first provide the multiple-unit semiconductor device that does not form sidewall, described multiple-unit semiconductor device comprises the first element region I and the second element region II.
Wherein, the first element region I comprises the first substrate 301, is positioned at the first grid dielectric layer 302 on the first substrate 301 surfaces, is positioned at the first grid electrode 303 on first grid dielectric layer 302 surfaces.Described first grid electrode 303 is over etching location, therefore the first substrate 301 be positioned at the part of its both sides will be as source and drain areas, and described first grid dielectric layer 302 is not yet aimed at through over etching, therefore is covered in the surface of above-mentioned source and drain areas.
The second element region II comprises the second substrate 401, is positioned at the second gate dielectric layer 402 on the second substrate 401 surfaces, is positioned at the second gate electrode 403 on second gate dielectric layer 402 surfaces.Same described second gate electrode is also located through over etching, the second substrate 401 is positioned at the part of its both sides as source and drain areas, and second gate dielectric layer 402 is not yet aimed at through over etching, therefore be covered in the surface of above-mentioned source-drain area, and the thickness of described second gate dielectric layer 402 is greater than the thickness of described first grid dielectric layer 302.In addition second gate dielectric layer 302 be positioned at second gate electrode bottom a side also by selective oxidation technology (LOCOS), the selective oxidation that carries out is grown, so thickness is thicker than other parts, plays buffer action.
As shown in Figure 8, on the surface of above-mentioned multiple-unit semiconductor device, also namely the surface coverage of the first element region I and the second element region II deposits insulating medium layer 500.
Described insulating medium layer 500 is used for the subsequent technique etching and forms sidewall, and its material is selected according to the needs of required formation sidewall, can also can be silicon nitride for silica, can form by chemical vapour deposition (CVD).Because in the aforementioned structure, first grid dielectric layer 302 and second gate dielectric layer 402 are all aimed at without over etching and be covered in the separately surface of source-drain area, therefore described insulating medium layer 500 also covers each the gate dielectric layer surface that is positioned on the source-drain area.In follow-up sidewall etching, each gate dielectric layer on the described source-drain area will with insulating medium layer 500 removal that is etched in the lump.
As shown in Figure 9, in vertical direction described insulating medium layer 500 is carried out the first plasma etching, described the first plasma etching carries out in the first element region I and the second element region II simultaneously.
Described the first plasma etching etch rate in the vertical direction is greater than side direction, so insulating medium layer 500 is will be on the vertical interface of gate electrode residual and form sidewall.In the present embodiment, because the thinner thickness of the first grid dielectric layer 302 among the first element region I, it is also less that the size of whole grid structure is compared the second element region II, therefore the first grid dielectric layer 302 on substrate 301 surfaces and insulating medium layer 500 removal that will be etched at first among the first element region I, and expose the source-drain area surface.Therefore described the first plasma etching is namely surperficial for stopping foundation with the source transistor drain region that exposes among the first element region I.After the first plasma etching finishes, will form comparatively desirable the first side wall 501 among the first element region I.And there are second gate dielectric layer 402 and a SI semi-insulation dielectric layer 500 in the surface of source-drain area with residual among the second element region I, and its sidewall is not yet finished.
As shown in figure 10, form mask layer 600 on the surface of described the first element region I.
Because the relative area of the first element region I is larger, therefore described mask layer 600 can be photoresist.Only need at the surface-coated photoresist of whole multiple-unit semiconductor device, then adopt mask exposure and development, so that the photoresist on the first element region I surface is retained.Above-mentioned mask layer 600 will protect the first element region I not to be subjected to the impact of subsequent technique.
As shown in figure 11, in vertical direction the insulating medium layer 500 that is positioned at the second element region II surface is carried out the second plasma etching, in the second element region II, to form the second sidewall 502.
Owing to passed through the first plasma etching, therefore the insulating medium layer 500 on the second element region II surface is by preliminary etching, the thickness of second gate dielectric layer 402 and the size of grid structure in respect to the second element region II, the etch amount of above-mentioned the first plasma etching is not enough to form the second sidewall 502.Therefore described the second plasma etching will further be removed the second gate dielectric layer 402 on source-drain area surface and residual insulating medium layer 500 as a supplement.Described the second plasma etching also should be to expose among the second element region II transistorized source-drain area surface for stopping foundation.After the second plasma etching is finished, should form the second desirable sidewall 502 among the second element region II.Because the protective effect of mask layer 600, described the second plasma etching can't be to the first element region I injury.
As shown in figure 12, remove the mask layer 600 on the first element region I surface.Finish the sidewall formation method of the described multiple-unit semiconductor device of present embodiment.
Above-described embodiment, only carry out step etching take two kinds of different element regions of gate dielectric layer thickness and form separately desirable sidewall as example, further, when described multiple-unit semiconductor device comprises the components and parts zone of different gate dielectric layer thickness more than three or three, also can adopt sidewall formation method of the present invention.Only need carry out the plasma etching with the number of times such as the number of partitions, and according to the ordering of each district's gate dielectric layer thickness, carry out successively etching, and be aided with the protection of mask layer for the element region that forms desirable sidewall.For example, for the sort element region of N of gate dielectric layer thickness, it will be subject to the plasma etching of N number, revise one by one the final comparatively desirable side wall construction that obtains.Those skilled in the art should be easily according to disclosed content, and the processing step that further pushes away specifically repeats no more herein.
Although the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.
Claims (6)
1. the sidewall formation method of a multiple-unit semiconductor device is characterized in that, comprising:
The multiple-unit semiconductor device that does not form sidewall is provided, described multiple-unit semiconductor device comprises the first element region and the second element region at least, and transistorized gate dielectric layer thickness is different in each element region, wherein, in described the first element region transistorized gate dielectric layer thickness less than transistorized gate dielectric layer in the second element region;
Surface coverage deposition insulating medium layer at described each element region of multiple-unit semiconductor device;
In vertical direction described insulating medium layer is carried out the first plasma etching, until expose in the first element region till the transistorized source-drain area surface, so that form the first side wall in the first element region;
Surface at the first element region forms mask layer;
In vertical direction the described insulating medium layer that is positioned at the second element region surface is carried out the second plasma etching, so that form the second sidewall in the second element region.
2. formation method as claimed in claim 1 is characterized in that, described insulating medium layer material is silica or silicon nitride.
3. formation method as claimed in claim 2 is characterized in that, described insulating medium layer adopts chemical vapour deposition (CVD) to form.
4. formation method as claimed in claim 1 is characterized in that, described mask layer material is photoresist.
5. formation method as claimed in claim 1 is characterized in that, described the insulating medium layer that is positioned at the second element region surface is carried out the second plasma etching, until expose in the second element region till the transistorized source-drain area surface.
6. formation method as claimed in claim 1 also comprises the step of the mask layer of removing the first element region surface.
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| CN1841706A (en) * | 2005-03-29 | 2006-10-04 | 冲电气工业株式会社 | Manufacturing method of semiconductor device |
| CN1917173A (en) * | 2005-08-16 | 2007-02-21 | 力晶半导体股份有限公司 | Fabrication method of gate dielectric layer |
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Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Co-patentee before: Wuxi Huarun Shanghua Technology Co., Ltd. Patentee before: Wuxi CSMC Semiconductor Co., Ltd. |